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参数资料
| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 19/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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MTA85XXX
DS40115C-page 26
1995 Microchip Technology Inc.
12.0
RESET
The PIC16C5X differentiates between various kinds of
resets:
Power-On Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT time-out reset
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in all
other resets. Most other registers are reset to a “reset
state” on Power-On Reset (POR), MCLR or a WDT
reset. Note that the PIC16C5X does not differentiate
between a WDT reset during SLEEP or during normal
operation. The TO and PD bits are set or cleared
depending upon the reset situation (Table 12-1). These
bits may be used to determine the nature of the reset.
See Table 12-3 for a full description of reset states of all
registers.
Figure 12-1 shows the simplified block diagram of the
on-chip reset circuit.
12.1
Power-On Reset (POR) and Device-
Reset Timer (DRT)
12.1.1
POWER-ON RESET (POR)
The PIC16C5X family incorporates an on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations. To use this fea-
ture the user merely needs to tie the MCLR/VPP pin to
VDD. Figure 12-8 shows the electrical structure of
TMR0 inputs. The Power-On Reset circuit and the
Device Reset Timer circuit are closely related. On
power-up the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset-latch and thus end the on-
chip reset signal.
Figure 12-2
and
Figure 12-3
are
two
power-up
situations with relatively fast rise time on VDD. VDD is
allowed to rise and stabilize (Figure 12-2) before
bringing MCLR high. The chip will actually come out of
reset (TDRT msec) after MCLR goes high. The on-chip
Power-On Reset feature (Figure 12-3) is being used
(MCLR and VDD are tied together). VDD is stable before
the start-up timer times out and there is no problem in
getting a proper reset. Figure 12-4 depicts a potentially
problematic situation where VDD rises too slowly. In this
situation, when the start-up timer times out, VDD has
not reached the VDD (min) value and the chip is, there-
fore, not guaranteed to function correctly.
To summarize, the on-chip POR is guaranteed to work
if the rate of rise of VDD is no slower than 0.05V/ms, and
VDD starts from 0V. The on-chip POR time delay is too
short for low frequency crystals which require much
longer than 18 ms to start-up and stabilize. For such sit-
uations, we recommend that external RC circuits be
used to achieve longer POR delay times.
FIGURE 12-1: ON-CHIP RESET CIRCUIT BLOCK DIAGRAM
SQ
R
Q
VDD
MCLR/VPP pin
Power-Up
Detect
On-Chip
RC OSC
POR (Power-On Reset)
WDT Time-out
RESET
CHIP RESET
8-bit Async
Ripple Counter
(Start-up Timer)
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