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参数资料
| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 7/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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1995 Microchip Technology Inc.
DS40115C-page 15
MTA85XXX
5.6.1
CARRY/BORROW AND
DIGIT CARRY/BORROW BITS:
The carry bit (C) is a carry out in addition operation
(ADDWF) and a borrow out in subtract operation
(SUBWF).
It is also affected by RRF and RLF instructions. The
following examples explain carry/borrow bit operation:
;SUBWF Example #1
;
clrf
0x1f
;f(1fh)=0
movlw
1
;wreg=1
subwf
0x1f
;f(1fh) =f(1fh)- wreg
;=0-1=FFh
;Carry=0: Result is
;negative
;
;SUBWF Example #2
movlw
0xFF
;
movwf
0x1F
;f(0x1F)=FFh
clrw
;wreg=0
subwf
0x1F
;f(0x1F)=f(0x1F)- wreg
;=FFh-0=FFh
;Carry=1:Result is
;positive
;
The digit carry operates in the same way as the carry
bit, (i.e., it is a borrow in a subtract operation).
5.6.2
TIME OUT AND POWER DOWN STATUS
BITS (TO, PD)
The TO and PD bits (STATUS<4:3>) can be tested to
determine if a RESET condition has been caused by a
Watchdog Timer time-out, a power-up condition, or a
wake-up from SLEEP by the Watchdog Timer or MCLR
pin.
These status bits are only affected by events listed in
Table 5-2.
TABLE 5-2:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
TO
PD
Remarks
Power-Up
11
No effect on PD
WDT Time-out
0x
SLEEP instruction
10
CLRWDT instruction
11
Note 1: A WDT time-out will occur regardless of the
status of the bit TO. A SLEEP instruction
will be executed, regardless of the status of
the PD bit. Table 5-3 reflects the status of
TO and PD after the corresponding event.
TABLE 5-3:
TO/PD STATUS AFTER
RESET
5.6.3
PROGRAM PAGE PRESELECT FOR
MTA858XX
Bits (STATUS <6:5>) are defined as page address bits
PA1:PA0 and are used to preselect a program memory
page. When executing a GOTO, CALL, or an instruc-
tion with PC as destination (e.g., MOVWF PC), PA1:PA0
are loaded into bit A10:A9 of the program counter,
selecting one of the available program memory pages.
The direct address specified in the instruction is only
valid within this particular memory page.
RETLW
instructions do not change the page preselect
bits.
Upon a RESET condition, PA2:PA0 are cleared to '0's.
5.7
File Select Register (FSR) f4
Bits (STATUS <4:0>) select one of the 32 available file
registers in the indirect addressing mode (that is,
calling for the INDF register in any of the file oriented
instructions).
Bit7 of the FSR is read-only and is always read as a '1'.
If no indirect addressing is used, the FSR can be used
as a 5-bit wide general purpose register.
Bits (STATUS <6:5>) of the FSR will always read as a
'1' for MTA854XX devices. For MTA858XX products,
bits (STATUS <6:5>) of the FSR will select the current
data memory bank (Figure 5-1).
The lower 16 bytes of each bank are physically
identical and are always selected when bit4 of the FSR
(in case of indirect addressing) is '0', or bit4 of the direct
file
register
address
of
the currently
executing
instruction is '0' (e.g., MOVWF DATAMEM).
Only if bit4 in the above mentioned cases is '1',
(STATUS <6:5>) of the FSR select one of the four
available
register
banks
with
16
bytes
each
(MTA858XX only).
TO
PD
Reset was caused by
00
WDT wake-up from SLEEP
01
WDT time-out (not during SLEEP)
10
MCLR wake-up from SLEEP
11
Power-up
uu
Low pulse on MCLR input
Note 1: The TO and PD bit maintain their status (u)
until an event of Table 5-2 occurs. A low
pulse on the MCLR input does not change
the TO and PD status bits.
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