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| 型号： | MTA85812S-10I/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 20/72页 |
| 文件大小： | 760K |
| 代理商： | MTA85812S-10I/SS |
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1995 Microchip Technology Inc.
DS40115C-page 27
MTA85XXX
12.1.2
DEVICE RESET TIMER (DRT)
The Device Reset Timer provides a fixed 18 ms
nominal time-out on RESET. The Device Reset Timer
operates with an internal RC oscillator. The processor
is kept in RESET as long as the DRT is active. The DRT
delay allows VDD to rise above VDD min., and allows
the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately
18 ms after the voltage on the MCLR/VPP pin has
reached a logic high (VIHMC) level. Thus, external RC
networks connected to the MCLR input are not required
in most cases, allowing for savings in cost-sensitive
and/or space restricted applications.
The Device Reset time delay will vary from chip to chip
and due to VDD, temperature, and process variation.
The DRT will also be triggered upon a WDT time-out.
This is particularly important for applications using the
WDT
to
waken
the
PIC16C5X
from
SLEEP
automatically.
12.1.3
TIME-OUT SEQUENCE
Table 12-2 lists the reset conditions for the special
function registers while Table 12-3 lists the reset
conditions for all the registers.
TABLE 12-1:
TO/PD STATUS AFTER
RESET
TO
PD
RESET was caused by
00
WDT wake-up from SLEEP
01
WDT time-out (not during SLEEP)
10
MCLR wake-up from SLEEP
11
Power-up
uu
= Low pulse on MCLR input
The TO and PD bits maintain their status (u) until a
reset occurs. A low-pulse on the MCLR input does
not change the TO and PD status bits.
TABLE 12-2:
RESET CONDITIONS FOR SPECIAL REGISTERS
Condition
STATUS
Addr: 03h
PCL
Addr: 02h
Power-On Reset
0001 1xxx
1111 1111
MCLR reset during normal operation
000u uuuu(1)
1111 1111
MCLR reset during SLEEP
0001 0uuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset during normal operation
0000 1uuu
1111 1111
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1:
The TO and PD bits retain their last value until one of the other reset conditions occur.
2:
The CLRWDT instruction will set the TO and PD bits
TABLE 12-3:
RESET CONDITIONS FOR ALL REGISTERS
Register
Address
Power-on Reset
MCLR or WDT Reset
W
N/A
xxxx xxxx
uuuu uuuu
TRIS
N/A
1111 1111
OPTION
N/A
--11 1111
INDF
00h
—
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
STATUS
03h
0001 1xxx
000? ?uuu (1)
FSR
04h
xxxx xxxx
uuuu uuuu
PORTA
05h
---- xxxx
---- uuuu
PORTB
06h
xxxx xxxx
uuuu uuuu
PORTC
07h
xxxx xxxx
uuuu uuuu
General Purpose
register files
08-7Fh
xxxx xxxx
uuuu uuuu
Legend: u = unchanged,
x = unknown,
-
= unimplemented read as '0',
? = value depends on condition.
Note 1:
See Table 12-2 for reset value for specific conditions.
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