参数资料
| 型号： | NCN6000DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 产品变化通告： | Product Obsolescence 01/Jul/2009 |
| 标准包装： | 1 |
| 应用： | ATM 终端，气泵，ISM |
| 接口： | 微控制器 |
| 电源电压： | 2.7 V ~ 6 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 剪切带 (CT) |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
22
Vbat Supply Voltage Monitoring
The builtin comparator, associated with the band gap
reference, continuously monitors the +Vbat input. During
the start up, all the NCN6000 functions are deactivated and
no data transfer can take place. When the +Vbat voltage rises
above 2.35 V (typical), the chip is activated and all the
functions becomes available. The typical behavior is
provided here after Figure 16. At this point, the internal
Power On Reset signal is activated (not accessible
externally) and all the logic signals are forced into the states
as defined by Table 3.
If the +Vbat voltage drops below 2.25 V (typical) during
the operation, the NCN6000 generate a Power Down
sequence and is forced in a no operation mode. The builtin
100 mV (typical) hysteresis avoids unstable operation when
the battery voltage slowly varies around the 2.30 V.
On the other hand, the microcontroller can read the
STATUS signal, pin 5, to control the state of the battery prior
to launch either a NCN6000 programming or an ATR
sequence (Table 4).
2.80 V
Figure 16. Typical Vbat Monitoring
Vbat
2.35 V
2.25 V
3.30 V
Vbat_OK
Vbat STATUS
Note: Drawing is not to scale and voltages are typical.
See specifications data for details.
DCDC Converter Operation
The builtin DCDC converter is based on a modified
boost structure to cover the full battery and card operating
voltage range. The builtin battery voltage monitor provides
an automatic system to accommodate the mode of operation
whatever be the Vbat and CRD_VCC voltages. Comparator
U3/Figure 17 tracks the two voltages and set up the
operating mode accordingly.
U2
+
U3
Vref
+
MOS Drive
Substrat Bias
U1
PWR_ON
3 V/ 5 V
Overload
VCC_OK
R1
1R
Current Sense
20
19
18
15
17
Vbat
L2
22
mH
Lout_L
Lout_H
+
GND
CRD_VCC
C1
GND
Vout_3_5
Vref_3/5 V
Voltage Regulation
Vbat
Q3
Q1
Q2
GND
Vbat
Vbat/VCC Comparator
NMOS Gate Drive
PMOS Gate Drive
LOGIC
CONTROL
GND
PWR_GND
GND
Figure 17. Basic DCDC Structure
+
R2
R3
R4
Active Pull Down
GND
Q4
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