参数资料
| 型号： | NCN6000DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 34/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 产品变化通告： | Product Obsolescence 01/Jul/2009 |
| 标准包装： | 1 |
| 应用： | ATM 终端，气泵，ISM |
| 接口： | 微控制器 |
| 电源电压： | 2.7 V ~ 6 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 剪切带 (CT) |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
7
PIN FUNCTIONS AND DESCRIPTION (continued)
Pin
Description
Type
Name
8
I/O
Input/Output
Pull Up
This pin is connected to an external microcontroller interface. A bidirectional level translator
adapts the serial I/O signal between the smart card and the microcontroller. The level
translator is enabled when CS = L. The signal present on this pin is latched when CS = H.
9
INT
OUTPUT
Pull Down
This pin is activated LOW when a card has been inserted and detected by the interface or
when the NCN6000 reports Vbat or CRD_VCC status (See Table 6). The signal is reset to
a logic 1 on the rising edge of either CS or PWR_ON. The Collector open mode makes
possible the wired AND/OR external logic. When two or more interfaces share the INT
function with a single microcontroller, the software must poll the STATUS pin to identify the
origin of the interrupt (Figure 5).
10
CLOCK_IN
CLOCK INPUT
High Impedance
This pin can be connected to either the microcontroller master clock, or to any clock signal,
to drive the external smart cards. The signal is fed to internal clock selector circuit and
translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4 or 8,
Care must be observed, at PCB level, to minimize the pickup noise coming from the
CLOCK_IN line. It is recommended to put a shield, built with a 10 mil copper track, around
this line and terminated to the GND.
11
CRD_DET
INPUT
The signal coming from the external card connector is used to detect the presence of the
card. A builtin pull up low current source makes this pin active LOW or HIGH, assuming
one side of the external switch is connected to ground. At Vbat start up, the default
condition is Normally Open switch, negative going insertion detection. The Normally
Closed switch, positive going insertion detection, can be defined by programming the
NCN6000 accordingly. In this case, the polarity must be set up during the first cycles of the
system initialization, otherwise an already inserted card will not be detected by the chip.
12
CRD_RST
OUTPUT
This pin is connected to the RESET pin of the card connector. A level translator adapts the
RESET signal from the microcontroller to the external card. The output current is internally
limited to 15 mA. The CRD_RST is validated when PWR_ON = H and PGM = H and hard
wired to Ground when the card is deactivated.
13
CRD_CLK
OUTPUT
This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes
from the clock selector circuit output. Combining A0, A1, PGM and I/O, as depicted in
Table 3 and Figure 3, programs the clock selection. This signal can be forced into a
standby mode with CRD_CLK either High or Low, depending upon the mode defined by
Care must be observed, at PCB level, to minimize the pickup noise coming from the
CRD_CLK line. It is recommended to put a shield, built with a 10mil copper track, around
this line and terminated to the GND.
14
CRD_IO
I/O
This pin handles the connection to the serial I/O pin of the card connector. A bidirectional
level translator adapts the serial I/O signal between the card and the microcontroller. The
CRD_IO pin current is internally limited to 15 mA. A builtin register holds the previous
state presents on the I/O input pin.
15
CRD_VCC
POWER
This pin provides the power to the external card. It is the logic level “1” for CRD_IO,
CRD_RST and CRD_CLK signals. The energy stored by the DCDC external inductor
Lout must be smoothed by a 10
mF capacitor, associated with a 100 nF ceramic in parallel,
connected across CRD_VCC and GND. In the event of a CRD_VCC UVLOW voltage, the
NCN6000 detects the situation and feedback the information in the STATUS bit. The device
does not take any further action, particularly the DCDC converter is neither stopped nor
reprogrammed by the NCN6000. It is up to the external MPU to handle the situation.
However, when the CRD_VCC is overloaded, the NCN6000 shut off the DCDC converter,
pulls the INT pin Low and reports the fault in the STATUS register.
16
GROUND
SIGNAL
The logic and low level analog signals shall be connected to this ground pin. This pin must
be externally connected to the PWR_GND pin 17. The designer must make sure no high
current transients are shared with the low signal currents flowing into this pin.
17
PWR_GND
POWER
This pin is the Power Ground associated with the builtin DCDC converter and must be
connected to the system ground together with GROUND pin 11. Using good quality ground
plane is recommended to avoid spikes on the logic signal lines.
18
Lout_L
POWER
The High Side of the external inductor is connected between this pin and Lout_H to provide
the DCDC function. The builtin MOS devices provide the switching function together with
the CRD_VCC voltage rectification.
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| NCN6001/D | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Compact Smart Card Interface IC |
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