参数资料
| 型号： | NCN6000DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 产品变化通告： | Product Obsolescence 01/Jul/2009 |
| 标准包装： | 1 |
| 应用： | ATM 终端，气泵，ISM |
| 接口： | 微控制器 |
| 电源电压： | 2.7 V ~ 6 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 剪切带 (CT) |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
6
ABBREVIATIONS
Lout_H
DCDC External Inductor
Lout_L
DCDC External Inductor
Cout
Output Capacitor
VCC
Card Power Supply Input
Icc
Current at CRD_VCC Pin
Class A
5.0 V Smart Card
Class B
3.0 V Smart Card
CS
Chip Select (from MPU)
Z
High Impedance Logic State
(according to ISO7816)
CRD_VCC
Interface IC Card Power Supply Output
CRD_CLK
Interface IC Card Clock Output
CRD_RST
Interface IC Card Reset Output
CRD_IO
Interface IC Card I/O Signal Line
CRD_DET
Interface IC Card Detection
ATR
Answer to Reset
PGM
Select Programming or Normal Operation
INT
Interrupt (to MPU)
tr
Rise Time
tf
Fall Time
td
Delay Time
ts
Storage Time
PIN FUNCTIONS AND DESCRIPTION
Pin
Name
Type
Description
1
A0
INPUT
This pin is combined with A1, PGM, RESET and I/O to program the chip mode of operation
2
A1
INPUT
This pin is combined with A0, PGM, RESET and I/O to program the chip mode of operation
3
PGM
INPUT
This pin is combined with A0, A1, RESET and I/O to program the chip mode of operation
4
PWR_ON
INPUT
Pull Down
This pin validates the operation of the internal DCDC converter:
CS = L + PWR_ON = Negative going: DCDC is OFF
CS = L + PWR_ON = Positive going: DCDC is ON
Note: The PWR_ON bit must be combined with a Low state CS signal to activate
the function. (Table 2)
5
STATUS
OUTPUT
This pin provides logic state related to the card and NCN6000 status. According to the A0,
A1 and PGM logic state, this pin carries either the Card present status or the Vbat or the
DCDC operation state. When PGM = L, STATUS is not affected, see Table 2.
6
CS
INPUT
Pull Up
This pin provides the NCN6000 chip select function. The PWR_ON, RESET, I/O, A0, A1 and
PGM signals are disabled when CS = H. When PGM = L and CS = L, the device jumps to
unique physical address when more than one card are controlled by a single MPU. The data
presented by the MPU are latched upon positive going edge of the Chip Select pin.
7
RESET
INPUT
Pull Down
This pin provides two modes of operation depending upon the logic state of PGM pin 3:
PGM = 1: The signal present at this pin is translated to pin 12 (card reset
signal) when CS = L and PWR_ON = H. It is latched when CS = H.
PGM = 0: The signal present on this pin is used as a logic input to program the
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