参数资料
| 型号： | NCN6000DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 产品变化通告： | Product Obsolescence 01/Jul/2009 |
| 标准包装： | 1 |
| 应用： | ATM 终端，气泵，ISM |
| 接口： | 微控制器 |
| 电源电压： | 2.7 V ~ 6 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 剪切带 (CT) |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
11
SMART CARD SECTION (25
°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol
Pin
Min
Typ
Max
Unit
CRD_RST @ CRD_VCC = +5.0 V
Output RESET VOH @ Icrd_rst = 20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
CRD_RST @ Vcc = +3.0 V
Output RESET VOH @ Icrd_rst = 20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
VOH
VOL
tR
tF
VOH
VOL
tR
tF
12
CRD_VCC 0.9
0
CRD_VCC 0.9
0
CRD_VCC
0.4
100
CRD_VCC
0.4
100
V
ns
V
ns
CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V
CRD_VCC = +5.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50%
"1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = 20 mA
Output VOL @ Icrd_clk = 100 mA
CRD_VCC = +3.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50%
"1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = 20 mA @ Cout = 30 pF
Output VOL @ Icrd_clk = 100 mA @ Cout = 30 pF
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
13
45
3.15
0
40
1.85
0
5.0
55
18
CRD_VCC
+0.5
5.0
60
18
CRD_VCC
0.7
MHz
%
ns
V
MHz
%
ns
V
CRD_I/O @ CRD_VCC = +5.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = 20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
CRD_I/O @ CRD_VCC = +3.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = 20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
FIO
TRIO
TFIO
VOH
VOL
FIO
TRIO
TFIO
VOH
VOL
14
CRD_VCC 0.9
0
CRD_VCC 0.9
0
315
0.8
CRD_VCC
0.4
0.8
CRD_VCC
0.4
kHz
ms
V
kHz
ms
V
CRD_IO Pull Up Resistor @ PWR_ON = H
RCRDPU
14
20
26
k
W
Card Detection Debouncing Delay:
Card Insertion
Card Extraction
TCRDIN
TCRDOFF
11
50
150
ms
Card Insertion or Extraction Positive Going Input
High Voltage
VIHDET
11
0.70 * Vbat
Vbat
V
Card Insertion or Extraction Negative Going Input
Low Voltage
VILDET
11
0
0.30 * Vbat
V
Card Detection Bias Pull Up Current @
Vbat = 5.0 V
IDET
11
10
mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_iorst
12, 14
15
mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_clk
13
70
mA
8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over
the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.
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