参数资料
| 型号： | NCN6000DTBR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/36页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE SMART CARD 20TSSOP |
| 产品变化通告： | Product Obsolescence 01/Jul/2009 |
| 标准包装： | 1 |
| 应用： | ATM 终端，气泵，ISM |
| 接口： | 微控制器 |
| 电源电压： | 2.7 V ~ 6 V |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 剪切带 (CT) |
| 安装类型： | 表面贴装 |
| 其它名称： | NCN6000DTBR2GOSCT |
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NCN6000
http://onsemi.com
13
Card VCC, Card CLOCK and Card Detection
Polarity Programming
The CRD_VCC and CLOCK_IN programming options
allows matching the system frequency with the card clock
frequency, and to select 3.0 V or 5.0 V CRD_VCC supply.
The CRD_DET programming option allows the usage of
either Normally Open or Normally Close detection switch.
Table 3 highlights the A0, A1, PGM and I/O logic states for
the possible options. The default power up reset condition
is state 1: asynchronous clock, ratio 1/1, CRD_CLK
active, CRD_DET = Normally Open, CRD_VCC = 3.0 V.
All states are latched for each output variable in
programming mode at the positive going slope of Chip
Select [CS] signal. It is the system designer’s responsibility
to set up the options needed to match the chip with the
peripherals. In particular, when using Normally Close
switch, the CRD_DET polarity must be defined during the
first cycles of the initialization.
Table 3. Card VCC, Card Clock and Card Detection Polarity Truth Table
HEXA
CS
PWR_ON
PGM
RESET
A1
A0
I/O
CRD_VCC
CRD_CLK
CRD_DET
STATUS
$00
L
L
3.0 V
CLOCK_IN 1/1
H (Note 13)
$01
L
L
H
3.0 V
CLOCK_IN 1/2
H (Note 13)
$02
L
L
H
L
3.0 V
CLOCK_IN 1/4
H (Note 13)
$03
L
L
H
3.0 V
CLOCK_IN 1/8
H (Note 13)
$04
L
L
H
L
5.0 V
CLOCK_IN 1/1
H (Note 13)
$05
L
L
H
L
H
5.0 V
CLOCK_IN 1/2
H (Note 13)
$06
L
L
H
L
5.0 V
CLOCK_IN 1/4
H (Note 13)
$07
L
L
H
5.0 V
CLOCK_IN 1/8
H (Note 13)
$08
L
L
H
L
START
H (Note 13)
$09
L
L
H
L
H
STOP Low
H (Note 13)
$0A
L
L
H
L
H
L
STOP High
H (Note 13)
$0B
L
L
H
L
H
Reserve
H (Note 13)
$0C
L
L
H
L
Normally Open
(Note 12)
H (Note 13)
$0D
L
L
H
L
H
Normally Close
(Note 12)
H (Note 13)
$0E
L
L
H
L
Normally Close
(Note 12)
H (Note 13)
$0F
L
L
H
Normally Close
Note 12)
H (Note 13)
$10
L
H
Z
L
Z
Card Present
$12
L
1
H
Z
L
H
Z
DCDC status
$14
L
H
Z
H
L
Z
Vbat
$16
L
1
H
Z
H
Z
CRD_VCC
9. The programmed conditions are latched upon the Chip Select (CS, pin 6) positive going transient.
10. Card clock integrity is guaranteed no spikes whatever be the frequency switching.
11. The STATUS register is not affected when the NCN6000 operates in any of the programming functions.
12. The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address.
13. The High Level on STATUS in registers $00 to $0F, inclusive, having being implemented to reduce current consumption but have no other
meanings.
14. At turn on, the NCN6000 is initialized with CRD_VCC = 3.0V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open.
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