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参数资料
| 型号： | ORSO42G5-2BMN484I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 110/153页 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
6
setup/hold and clock to out performance.
New Double-Data Rate (DDR) and zero-bus turn-around (ZBT) memory interfaces support the latest high-speed
memory interfaces.
New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal
logic.
ispLEVER development system software. Supported by industry-standard CAE tools for design entry, synthe-
sis, simulation, and timing analysis.
Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-PHY3.
Description
What Is an FPSC?
FPSCs, or Field-Programmable System Chips, are devices that combine eld-programmable logic with ASIC or
mask-programmed logic on a single device. FPSCs provide the time to market and the exibility of FPGAs, the
design effort savings of using soft Intellectual Property (IP) cores, and the speed, design density, and economy of
ASICs.
FPSC Overview
Lattice’s Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of
Programmable Logic Cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded
logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efciency, none of the
FPGA functionality is changed—all of the Series 4 FPGA capability is retained: Embedded Block RAMs, MPI,
PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing
pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins
retain their FPGA functionality.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates.
Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count
is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-
area efcient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
ORCA Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-
master 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA
logic functions including the Embedded Block RAMs and the MicroProcessor Interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system exibility, FPGA conguration RAMs are available for use by the embedded core. This
supports user-programmable options in the embedded core, in turn allowing for greater exibility. Multiple embed-
ded core congurations may be designed into a single device with user-programmable control over which congu-
rations are implemented, as well as the capability to change core functionality simply by reconguring the device.
相关PDF资料 |
PDF描述 |
|---|---|
| ORSO42G5-1BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| VE-B03-IX-F1 | CONVERTER MOD DC/DC 24V 75W |
| MS27467T25A61PA | CONN PLUG 61POS STRAIGHT W/PINS |
| MS27467E25A61PA | CONN PLUG 61POS STRAIGHT W/PINS |
| MS27467E25B61PC | CONN PLUG 61POS STRAIGHT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO42G5-3BM484C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO42G5-EV | 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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