参数资料
型号: ORSO42G5-2BMN484I
厂商: Lattice Semiconductor Corporation
文件页数: 91/153页
文件大小: 0K
描述: IC TRANCEIVERS FPSC 680FPGAM
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 60
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
42
SONET Mode Block Alignment – ORSO82G5
Figure 28 describes the clocks and recommended clocking for block alignment in the SONET mode. For block
alignment, the low speed portion for each block should be sourced by a single clock. As the gure shows, for block
A, RSYSCLKA1 and RSYSCLKA2 should be sourced by RCK78A. For block B, RSYSCLKB1 and RSYSCLKB2
should be sourced by RCLK78B. RCLK78A can be sourced by any channel in block A and RCLK78B can be
sourced by any channel in block B.
Figure 28. Receive Clocking Diagram for Four-Channel Alignment in Block A – ORSO82G5
SONET Mode Octal Alignment – ORSO82G5
Figure 29 shows the clocking scheme for eight-channel alignment. In this application, all four clocks RSYSCLKA1,
RSYSCLKA2, RSYSCLKB1 and RSYSCLKB2 should be sourced from a common clock. Either RCK78A or
RCK78B can be used as a common clock source. The gure shows RCK78A being used as the clock source.
FPGA
RCK78A
SPE
Generator
SPE
Generator
SPE
Generator
SPE
Generator
Alignment
FIFO
Alignment
FIFO
Alignment
FIFO
Alignment
FIFO
Framer,
Descrambler
Framer,
Descrambler
Framer,
Descrambler
Framer,
Descrambler
DEMUX
RSYSCLKA1
Logic Common to Block
REFCLKA[P,N]
(155.52 MHz)
Channel AA
Channel AB
HDIN[P:N]_AA
2.488 Gbits/s
HDIN[P:N]_AB
2.488 Gbits/s
RSYSCLKA2
Channel AC
Channel AD
RWCKAD
RWCKAA
HDIN[P:N]_AA
2.488 Gbits/s
HDIN[P:N]_AB
2.488 Gbits/s
SERDES
DEMUX
SERDES
DEMUX
SERDES
DEMUX
SERDES
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