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| 型号： | ORSO42G5-2BMN484I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 82/153页 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPGAM |
| 产品变化通告： | Product Discontinuation 01/Aug/2011 |
| 标准包装： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
34
ment FIFO should be at exactly the same frequency (0 ppm difference), i.e., from a common clock source. Later in
this data sheet, Figures 22, 23, 27, 28, and 29 show the recommended clocking scheme to adhere to this require-
ment. In addition, supervisory features such as BIP error check, OOF check, RDI monitoring and AIS-L insertion
during OOF are also implemented. All the supervisory features are controlled through programmable register bits.
Framer
The frame and byte phase of the bits within the 32-bit word from the DEMUX is random. For each of the STS-48
channels, the framer outputs 4 bytes (32-bits) that are frame-aligned and a frame pulse that is one clock-wide. The
transition from A1 bytes to A2 bytes should happen on a 32-bit boundary. If any two consecutive bytes of the 4-
byte-aligned word match the A1-A2 pattern (0xF628 in standard SONET framing), the byte-aligned word will be
byte rotated to achieve frame alignment.
Framer State Machine (FSM)
The framer FSM is responsible for detecting the in-frame and Out-Of-Frame status of the incoming data and sends
out alarms (interrupts) on Out-Of-Frame (OOF). The framer is a pseudo-SONET framer in the sense that it does
not support LOF or SEF detect-alarm signal as specied in the GR-253 standard.
The framer has a fast frame mode where a single good framing pattern can cause the framer state machine to go
the “in_frm” state and a single bad frame can cause the state machine to declare “OOF” (See Fig. 19). The fast
frame mode can be set by the software register bit, FFRM_EN_xx.
The FSM is a four byte framer and searches for the framing pattern based on the 32-bit words. Accordingly, the
framing pattern is four A1 bytes (F6,F6,F6,F6) followed by four A2 bytes (28,28,28,28).
The framer FSM comes out of reset in the “OOF” state with the OOF alarm set. The framer goes in frame if it nds
2 consecutive frames with the desired framing bytes and goes out of frame if it nds 4 consecutive frames with at
least one framing bit error in each frame. Frame timing is also synchronized based on the STS-48 row and column
counters. This corresponds to SONET specication that it will take two consecutive valid framing patterns to frame
to an incoming signal. Outside the “OOF” state, the OOF alarm output is low.
Figure 19. Transmit Clocking Diagram in SONET Mode
pat_srch
reset
OOF=1
patdet & !ffm
new_frm
in_frm
patdet
OOF=0
!patdet
oof_one
oof_two
oof_three
Legend:
ffm ~ In fast frame mode
AND ffm
!ffm AND
patdet
!patdet
patdet
!patdet
patdet
!patdet
!ffm ~ In regular frame
mode
patdet ~ Correct 4A1/4A2
framing pattern
detected
!patdet ~ Correct 4A1/4A2
framing pattern
NOT detected
!patdet
patdet
相关PDF资料 |
PDF描述 |
|---|---|
| ORSO42G5-1BMN484C | IC TRANCEIVERS FPSC 680FPGAM |
| VE-B03-IX-F1 | CONVERTER MOD DC/DC 24V 75W |
| MS27467T25A61PA | CONN PLUG 61POS STRAIGHT W/PINS |
| MS27467E25A61PA | CONN PLUG 61POS STRAIGHT W/PINS |
| MS27467E25B61PC | CONN PLUG 61POS STRAIGHT W/PINS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO42G5-3BM484C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO42G5-EV | 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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