参数资料
型号: ORSO42G5-2BMN484I
厂商: Lattice Semiconductor Corporation
文件页数: 14/153页
文件大小: 0K
描述: IC TRANCEIVERS FPSC 680FPGAM
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 60
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
110
High Speed Data Receiver
Table 43 species receiver parameters measured on devices with worst case process parameters and over the full
range of operation conditions.
Table 43. External Data Input Specications
Input Data Jitter Tolerance
A receiver’s ability to tolerate incoming signal jitter is very dependent on jitter type. High speed serial interface stan-
dards have recognized the dependency on jitter type and have recently modified specifications to indicate toler-
ance levels for different jitter types as they relate to specific protocols. Sinusoidal jitter is considered to be a worst
case jitter type. Table 44 shows receiver specifications with 10 MHz sinusoidal jitter injection. Other jitter tolerance
measurements were measured in a separate experiment detailed in technical note TN1032, SERDES Test Chip Jit-
ter, and are not reected in these results.
Table 44. Receiver Sinusoidal Jitter Tolerance Specications
Parameter
Conditions
Min.
Typ.
Max.
Units
Input Data
Stream of Nontransitions
Scrambler off
72
Bits
Sensitivity (differential), worst-case
1
2.7Gbps
80
mVp-p
Input Levels
2
VSS - 0.3
VDD_ANA + 0.3
V
Internal Buffer Resistance (Each input to VDDIB)
40
50
60
Ω
PLL Lock Time
3
Note 2
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V to 1.575V sup-
ply.
2. Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2
3. The ORT82G5 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing rst bit, then byte
(character), then channel (32-bit word), and nally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the
time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream. If the PLL is unable to lock to the
serial data stream, it instead locks to REFCLK to stabilize the voltage-controlled oscillator (VCO), and periodically switches back to the
serial data stream to again attempt synchronization.
Parameter
Conditions
Max.
Unit
Input Data
Jitter Tolerance @ 2.7Gbps, Typical
600 mV diff eye
1
0.75
UIP-P
Jitter Tolerance @ 2.7Gbps, Worst case
600 mV diff eye
1
0.65
UIP-P
Jitter Tolerance @ 2.5Gbps,Typical
600 mV diff eye
1
0.79
UIP-P
Jitter Tolerance @ 2.5Gbps, Worst case
600 mV diff eye
1
0.67
UIP-P
1. With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, REFCLK jitter of 30 ps., TA = 0
oC to 85oC, 1.425V
to 1.575V supply. Jitter measured with a Wavecrest SIA-3000.
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