参数资料
型号: ORSO42G5-2BMN484I
厂商: Lattice Semiconductor Corporation
文件页数: 87/153页
文件大小: 0K
描述: IC TRANCEIVERS FPSC 680FPGAM
产品变化通告: Product Discontinuation 01/Aug/2011
标准包装: 60
系列: *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
39
Figure 24. Twin Channel Alignment – ORSO82G5
Figure 25. Alignment of SERDES Blocks A and B – ORSO82G5
Figure 26. Alignment of all Eight SERDES Channels – ORSO82G5
Each channel is provided with a 24 word x 33-bit FIFO. The FIFO can perform two tasks: (1) to change the clock
domain from receive clock to a clock from the FPGA side, and (2) to align the receive data over 2, 4, or 8 channels.
This FIFO allows a timing budget of 307 ns that can be allocated to skew between the data lanes and for transfer to
the common clock. The input to the FIFO consists of 32-bit data and a frame pulse that indicates the start of a
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t2
Channel AA
t1
t0
t3
TWIN ALIGNMENT OF CHANNELS AA AND AB
TWIN ALIGNMENT OF CHANNELS AC AND AD
TWIN ALIGNMENT OF CHANNELS BA AND BB
TWIN ALIGNMENT OF CHANNELS BC AND BD
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t1
t0
Channel AA
BLOCK ALIGNMENT OF CHANNELS AA
, AB, AC, AND AD
BLOCK ALIGNMENT OF CHANNELS BA
, BB, BC, AND BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
Channel AA
Channel AB
Channel AC
Channel AD
Channel BA
Channel BB
Channel BC
Channel BD
t0
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ORSO42G5-EV 功能描述:可编程逻辑 IC 开发工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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