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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 102/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
83
This section describes device I/O signals to/from the embedded core.
Table 41. FPSC Function Pin Descriptions
Symbol
I/O
Description
Common Signals for Both SERDES Quad A and B
PASB_RESETN
I
Active low reset for the embedded core. All non-SERDES specic registers
(addresses 308***, 309***, 30A***) in the embedded core are not reset.
1
PASB_TRISTN
I
Active low 3-state for embedded core output buffers.
1
PASB_PDN
I
Active low power down of all SERDES blocks and associated I/Os.
1
PASB_TESTCLK
I
Clock input for BIST and loopback test.
1
PBIST_TEST_ENN
I
Selection of PASB_TESTCLK input for BIST test.
1
PLOOP_TEST_ENN
I
Selection of PASB_TESTCLK input for loopback test.
1
PMP_TESTCLK
I
Clock input for microprocessor in test mode.
1
PMP_TESTCLK_ENN
I
Selection of PMP_TESTCLK in test mode.
1
PSYS_DOBISTN
I
Input to start BIST test.
1
PSYS_RSSIG_ALL
O
Output result of BIST test.
SERDES Quad A and B Pins
REFCLKN_A
I
CML reference clock input—SERDES quad A.
REFCLKP_A
I
CML reference clock input—SERDES quad A.
REFCLKN_B
I
CML reference clock input—SERDES quad B.
REFCLKP_B
I
CML reference clock input—SERDES quad B.
REXT_A
—
Reference resistor – SERDES quad A.
REXT_B
—
Reference resistor – SERDES quad B.
REXTN_A
—
Reference resistor – SERDES quad -. A 3.32 K W ± 1% resistor must be connected
across REXT_B and REXTN_B. This resistor should handle a current of 300 A.
REXTN_B
—
Reference resistor – SERDES quad B. A 3.32 K Ω ± 1% resistor must be con-
nected across REXT_B and REXTN_B. This register should handle a current of
300 A
HDINN_AA (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad A, channel A.
HDINP_AA (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad A, channel A.
HDINN_AB (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad A, channel B.
HDINP_AB (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad A, channel B.
HDINN_AC
I
High-speed CML receive data input – SERDES quad A, channel C.
HDINP_AC
I
High-speed CML receive data input – SERDES quad A, channel C.
HDINN_AD
I
High-speed CML receive data input – SERDES quad A, channel D.
HDINP_AD
I
High-speed CML receive data input – SERDES quad A, channel D.
HDINN_BA (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad B, channel A.
HDINP_BA (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad B, channel A.
HDINN_BB (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad B, channel B.
HDINP_BB (ORT82G5 only)
I
High-speed CML receive data input – SERDES quad B, channel B.
HDINN_BC
I
High-speed CML receive data input – SERDES quad B, channel C.
HDINP_BC
I
High-speed CML receive data input – SERDES quad B, channel C.
HDINN_BD
I
High-speed CML receive data input – SERDES quad B, channel D.
HDINP_BD
I
High-speed CML receive data input – SERDES quad B, channel D.
SERDES quad A and B Pins
HDOUTN_AA (ORT82G5 only)
O
High-speed CML transmit data output – SERDES quad A, channel A.
HDOUTP_AA (ORT82G5 only)
O
High-speed CML transmit data output – SERDES quad A, channel A.
HDOUTN_AB (ORT82G5 only)
O
High-speed CML transmit data output – SERDES quad A, channel B.
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