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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 47/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
33
grammed to a value > 0. (Default value is 0.) Change the value to 0 and check the OVFL bit again.
If OOS and OVFL are 1, then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising
edge. Two writes are required to the resync bits: write a 0 and then write a 1.
ORT82G5 Alignment Sequence
1.
Follow steps 1 and 2 in the start-up sequence described in a later section.
2.
Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that any changes to the
SERDES conguration bits should be followed by a software reset.
3.
Wait for 3 ms. REFCLK should be toggling by this time. During this time, congure the following registers.
Set the following bits in registers 30820, 30920
XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0 if the Fibre Channel state machine was
selected.
Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911.
FMPU_SYNMODE_xx. Set to appropriate values for 2, 4, or 8 alignment based on Table 7.
Set RCLKSEL[A:B] and TCKSEL[A:B] bits in registers 30A00.
RCKSEL[A:B] – Choose clock source for 78 MHz RCK78x (Table 18).
TCKSEL[A:B] – Choose clock source for 78 MHz TCK78x (Table 17). Send data on serial links.
Monitor the following status/alarm bits:
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130.
LKI-PLL_xx lock indicator. A 1 indicates that PLL has achieved lock.
Monitor the following status bits in registers 30804, 30904:
XAUISTAT_xx - In XAUI mode, they should be 10.
Monitor the following status bits in registers 30805, 30905
DEMUXWAS_xx-They should be 1 indicating word alignment is achieved.
CH248_SYNCxx-They should be 1 indicating channel alignment. This is cleared by resync.
4.
Write a 1 to the appropriate resync registers 30820, 30920 or 30A02. Note that this assumes that the previous
value of the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the
resync bits: write a 0 and then write a 1. It is highly recommended to precede a resync with a word alignment,
especially in situations where a disturbance in the receive SERDES path can cause misalignment of data and
OOS indications without bringing the FC/XAUI state machine to a loss of synch state. A word alignment is
achieved by writing a 0 and then a 1 to the appropriate DOWDALIGNxx bits in registers 30810/30910.
Check out-of-sync and FIFO overow status in registers 30814 (Bank A).
SYNC4_A_OOS, SYNC4_A_OVFL-by 4 alignment.
SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A1_OOS, SYNC2_A1_OVFL-by 2 alignment.
Check out-of-sync status in registers 30914 (Bank B).
SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment.
SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment.
Check out-of-sync status in register 30A03
SYNC8_OOS, SYNC8_OVFL-by 8 alignment.
If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again. If Out of
Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been programmed to
a value > 0. (Default value is 0.) Change the value to 0 and check the OVFL bit again. If OOS and OVFL are 1,
then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising edge. Two writes are
required to the resync bits: write a 0 and then write a 1.
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