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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 75/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
59
Table 26. Embedded Memory Slice Core/FPGA Interface Signal Description
Memory Maps
Denition of Register Types
The SERDES blocks within the ORT42G5 and ORT82G5 cores have a set of status and control registers for SER-
DES operation. There is also other group of status and control registers which are implemented outside the SER-
DES, which are related to the SERDES and other functional blocks in the FPSC core. (Addresses for the control
and status registers for the FPGA portion of the device are detailed in the ORCA Series 4 FPGAs data sheet,
which also describes the functions of those registers).
ORT42G5 Memory Map
Each ORT42G5 SERDES block has two independent channels. Each channel is identied by both a quad identi-
er, A or B, and a channel identier, C or D. (This naming convention follows that of the ORT82G5.) The registers in
ORT42G5 are 8-bit memory locations, which can be classied into Status Register and Control Register.
Status Register
Read-only register to convey the status information of various operations within the FPSC core. An example is the
state of the XAUI link-state-machine.
Control Register
Read-write register to set up the control inputs that dene the operation of the FPSC core.
Reserved addresses for the FPSC register blocks are shown in Table 29.
Table 27. Structural Register Elements
Table 28 details the memory map for the FPSC portion of the ORT42G5 device. In both Table 29 and Table 28, the
addresses are given as 18-bit hexadecimal (18’h) values. The address may be sourced either through the Micro-
Processor Interface or a User Master Interface. The MicroProcessor Interface (MPI) address bus is a 32-bit bus
FPGA/Embedded Core
Interface Signal Name]
Input (I) to or
Output (O)
from Core
Signal Description
Memory Slice Interface Signals
D_[A:B][35:0]
I
Data in—memory slice [A:B]
CKW_[A:B]
I
Write clock—memory slice [A:B].
CSWA_[A:B]
I
Write chip select for SRAM A—memory slice [A:B].
CSWB_[A:B]
I
Write chip select for SRAM B—memory slice [A:B].
AW_[A:B][10:0]
I
Write address—memory slice [A:B].
BYTEWN_[A:B][3:0]
I
Write control pins for byte-at-a-time write-memory slice [A:B].
Q_[A:B][35:0]
O
Data out—memory slice [A:B].
CKR_[A:B]
I
Read clock—memory slice [A:B].
CSR_[A:B]
I
Read chip select—memory slice [A:B]. CSR_[A:B]= 0 selects SRAM A.
CSR_[A:B]= 1 selects SRAM B.
AR_[A:B][10:0]
I
Read address—memory slice [A:B].
Address (0x)
Description
300xx
SERDES A, internal registers.
301xx
SERDES B, internal registers.
308xx
Channel A [C or D] registers (external to SERDES blocks).
309xx
Channel B [C or D] registers (external to SERDES blocks).
30A0x
Global registers (external to SERDES blocks).
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