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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 31/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
19
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplies both the signal
and the noise at the receiver
Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also
degrade the data eye opening at the receiver. In the ORT42G5 and ORT82G5 the degree of transmit preemphasis
can be programmed with a two-bit control from the microprocessor interface as shown in Table 3. The high-pass
transfer function of the preemphasis circuit is given by the following equation, where the value of a is shown in
H(z) = (1 – az
–1)
(1)
Table 3. Preemphasis Settings
Receive Path (Backplane to FPGA) Logic
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The retimed data are deserialized and presented as an 8-bit decoded or a
10-bit unencoded parallel data on the output port. The receiver also optionally recognizes comma characters,
detects code violations and aligns the bit stream to the proper word boundary.
As shown in Figure 6, the basic blocks in the receive path include:
Receive SERDES Block
CML input buffer
Receive PLL
1:10 demultiplexer (DEMUX)
Clock and Data Recovery (CDR) section
10b/8b decoder
1:4 demultiplexer and Embedded Core/FPGA interface
1:4 DEMUX
Low speed parallel Embedded Core/FPGA logic interface
Multi-channel alignment logic
PE1
PE0
Amount of Preemphasis (a)
0
0% (No Preemphasis)
0
1
12.5%
1
0
12.5%
1
25%
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