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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 88/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
70
SERDES Global Control Registers (Read Write) Act on all Four Channels in SERDES Quad A or SERDES Quad B.
30005 - A
30105 - B
[0]
Reserved
See
bit
descrip.
Reserved, must be set to 0. Set to 0 on device reset.
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the transmit and receive alarms
of all channels in the SERDES quad are prevented from generating an
interrupt (i.e., they are masked or disabled). The GMASK_[A:B] bit over-
rides the individual MASK_xx bits. GMASK_[A:B] = 1 on device reset.
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit provides the same function
as the hardware reset for the transmit and receive sections of all four
channels, except that the device conguration settings are not affected
when GSWRST_[A:B] is asserted. This is not a self-clearing bit. Once
set, this bit must be manually set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits. GSWRST_[A:B] = 0 on device
reset.
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When GPWRDNT_[A:B] = 1, sections of
the transmit hardware for all four channels of are powered down to con-
serve power. The GPWRDNT_[A:B] bit overrides the individual
PWRDNT_xx bits. GPWRDNT_[A:B] = 0 on device reset.
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When GPWRDNR_[A:B] = 1, sections of
the receive hardware for all four channels are powered down to conserve
power. The GPWRDNR_[A:B] bit overrides the individual PWRDNR_xx
bits. GPWRDNR_[A:B] = 0 on device reset.
[5]
Reserved
Reserved, 1 on device reset.
[6]
Not used
Not used. 0 on reset.
[7]
GTESTEN_[A:B]
Test Enable Control. When GTESTEN_[A:B] = 1, the transmit and
receive sections of all four channels are placed in test mode. The
GTESTEN_[A:B] bit overrides the individual TESTEN_xx bits.
GTESTEN_[A:B] = 0 on device reset.
30006 - A
30106 - B
[0:4]
TestMode[A:B]
00
TestMode - See Test Mode section for settings
[5]
Not used
[6:7]
Reserved
Control Registers (Read/Write), xx=[AA,...,BD]
30800 - Ax
30900 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
ENBYSYNC_xx
00
ENBYSYNC_xx = 1 Enables Receiver Byte Synchronization for Channel
xx. ENBYSYNC_xx = 0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
LCKREFN_xx
LCKREFN_xx = 0 Locks the receiver PLL to ref reference clock for
Channel xx.
LCKREFN_xx =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xx = 0 on device reset.
30801 - Ax
30901 - Bx
[0]xA
[1]xB
[2]xC
[3]xD
LOOPENB_xx
Enable Loopback Mode for Channel xx. When LOOPEN_xx=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xx=0 on device reset.
[4]xA
[5]xB
[6]xC
[7]xD
NOWDALIGN_xx
Word Align Disable Bit. When NOWDALIGN_xx=1, receiver word align-
ment is disabled for Channel xx. NOWDALIGN_xx=0 on device reset.
Table 30. ORT82G5 Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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相关代理商/技术参数 |
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|---|---|
| ORT43S | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCBC | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCG | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCO | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
| ORT43SBCBCBCR | 制造商:BOT 制造商全称:Bedford Opto Technology Ltd. 功能描述:3mm LED CIRCUIT BOARD INDICATOR 4 TIER SHROUDED |
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