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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 29/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
17
Embedded Core/FPGA Logic Interface and 4:1 Multiplexer
These blocks provide the data formatting and transmit data and clock signal transfers between the Embedded Core
and the FPGA Logic. Control and status registers in the FPGA portion of the chip contain to control the transmit
logic and record status. These bits are passed to the core using the FPGA System Bus and are described in later
sections of this data sheet.
The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The
data bytes are conveyed to the MUX via the TWDxx[31:0] ports (where xx represents the channel label [AA,...,BD]
or [AC, AD, BC, BD]). The control bits are TCOMMAx[3:0] which dene whether the input byte is to be interpreted
as data or as a special character and TBIT9xx[3:0] which are used to force a negative disparity present state. The
data and control signals are synchronized to the transmit clock, TSYS_CLK_xx. Both the data and control are
strobed into the core on the rising edge of TSYS_CLK_xx. Note that each TBIT9xx[3:0] controls the disparity of the
encoded version of its corresponding data byte. Setting bit TBIT9AC[3] to 1, for instance, will force the 8b/10b
encoder to assess a current negative running disparity state. This will cause it to encode TWDAC[31:24] positively
(more 1’s than 0’s). Setting TBIT9xx to 0 will leave the encoder free to alternate between positive and negative
encoding to maintain a zero running disparity.
The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to
10 bits of data/control at the SERDES transmit interface. The MUX has 2 clock domains - one based on the clock
received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES
clock. The time sequence of interleaving data/control values is shown in Figure 4.
Figure 4. Transmit MUX Block Timing - Single Channel
SERDES Block
The SERDES block accepts either 8-bit data to be encoded or 10-bit unencoded data at the parallel input port from
the MUX/DEMUX block. It also accepts the reference clock at the REFCLK_[A:B] input and uses this clock to syn-
thesize the internal high-speed serial bit clock.
The internal STBC311xx clock is derived from the reference clock. The frequency of this clock depends on the set-
ting of the half-rate/full-rate control bit setting the mode of the SERDES and the frequency of the REFCLK_[A:B]
and/or that of the high-speed serial data. A falling edge on the STBC311xx clock port will cause a new data charac-
ter to be transferred into the SERDES block. The latency from the SERDES block input to the high-speed serial
output is 5 STBC311xx clock cycles, as shown in Figure 5.
p
q
r
s
t
xyz
STBDxx[9:0]
LATENCY = 4 TSYS_CLK_xx CLOCKS
TWDxx[31:24],
TSYS_CLK_xx
s
8
r
8
z
8
y
8
10-bit wide data
TWDxx[23:16],
TWDxx[15:8],
r
7-0,
y
7-0,
TCOMMAxx[3]
TCOMMAxx[2]
TCOMMAxx[1]
TCOMMAxx[0]
TWDxx[7:0],
s
7-0,
z
7-0,
TBIT9xx[0]
TBIT9xx[1]
TBIT9xx[2]
TBIT9xx[3]
q
9
r
9
s
9
z
9
y
9
x
9
p
7-0,
p
8
t
7-0,
q
8
t
8
x
8
q
7-0,
x
7-0,
p
9
t
9
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