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| 型号： | ORT42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 53/119页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ORT42G5/CABLE/ADAPTER |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORT42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORT42G5EV |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
39
TCK78[A:B]:
This is a muxed output from the core to the FPGA across the core-FPGA interface of one of the 2 transmit SER-
DES clocks per block operating at up to 92.5 MHz in the embedded core. There is one clock output per SERDES
block.
TSYS_CLK[AC, AD, BC, BD]:
These clocks are inputs to the SERDES block A and B respectively from the FPGA. These are used by each chan-
nel to control the timing of the Transmit Data Path. To guarantee correct transmit operation theses clocks must be
frequency locked within 0 ppm to TCK78[A:B].
Transmit and Receive Clock Rates
Table 13 shows typical relationship between the data rates, the reference clock, the transmit TCK78[A:B] clock and
the receive RCK78[A:B] clock. The selection of full-rate or half-rate for a given reference clock speed is set by bits
in the transmit and receive control registers and can be set per channel.
Table 13. Transmit Data and Clock Rates
Besides taking in a TSYS_CLK_xx from the FPGA logic for each channel, the transmit path logic sends back a
clock of the same frequency, but arbitrary phase. This clock, TCK78[A:B], is derived from the MUX block of one of
the 2 channels in its SERDES block. The MUX blocks provide the potential source for TCK78[A:B] by a divide-by-4
of the SERDES STBC311xs clock used in synchronizing the transmit data words in the STBC311xx clock domain.
The STBC311xx clocks are internal to the core and are not brought across the core/FPGA interface
The receiver section receives high-speed serial data at its differential CML input port and sends in to the Clock and
Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKxx) and retimes the data.
Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[A:B] bit select the source channel of TCK78[A:B]. The selection of the source for TCK78[A:B] is con-
trolled by this bit as shown in Table 14.
Table 14. TCK78[A:B] Source Selection
Recommended Transmit Clock Distribution for the ORT42G5
As an example of the recommended clock distribution approach, TSYS_CLK_A[C or D] can be sourced by TCK78A
as shown in Figure 18 if the transmit line rate are common for both channels in a block. Similar clocking would be
used for Block B.
Data Rate
Reference Clock
TCK78[A: B] and RCK78[A:B]
Clocks
Rate of Channel
Selected as Clock
Source
0.6 Gbps
60 MHz
15 MHz
Half
1.0 Gbps
100 MHz
25 MHz
Half
1.25 Gbps
125 MHz
31.25 MHz
Half
2.0 Gbps
100 MHz
50 MHz
Full
2.5 Gbps
125 MHz
62.5 MHz
Full
3.125 Gbps
156 MHz
78 MHz
Full
3.7 Gbps
185 MHz
92.5 MHz
Full
TCKSEL[A:B]
Clock Source
0
Channel C
1
Channel D
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