参数资料
型号: P89LPC954FBD44,151
厂商: NXP Semiconductors
文件页数: 12/69页
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
标准包装: 160
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 40
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
2 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
2.2 Additional features
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
I Serial ash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
I Serial ash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
I In-Application Programming (IAP) of the ash code memory. This allows changing the
code in a running application.
I Low voltage (brownout) detect allows a graceful system shutdown when power fails.
May optionally be congured as an interrupt.
I Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
A (total power-down with voltage comparators disabled).
I On-chip power-on reset allows operation without external reset components. A
software reset function is also available.
I Programmable external reset pin (P1.5) conguration options: open drain bidirectional
reset input/output, reset input with pull-up, push-pull reset output, input-only port. A
reset counter and reset glitch suppression circuitry prevent spurious and incomplete
resets.
I Only power and ground connections are required to operate the P89LPC952/954
when internal reset option is selected.
I Congurable on-chip oscillator with frequency range options selected by user
programmed ash conguration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
I Programmable port output conguration options: quasi-bidirectional, open drain,
push-pull, input-only.
I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
I Four interrupt priority levels.
I Eight keypad interrupt inputs, plus two additional external interrupt inputs.
I Schmitt trigger port inputs.
I Second data pointer.
I Extended temperature range.
I Emulation support.
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