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参数资料
| 型号： | P89LPC954FBD44,151 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 26/69页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 16K 44LQFP |
| 标准包装： | 160 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 40 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LQFP |
| 包装： | 托盘 |
| 配用： | 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名称： | 568-7917 568-7917-ND 568-8269 935284303151 P89LPC954FBD44,151-ND P89LPC954FBD44-S P89LPC954FBD44-S-ND |
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P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
32 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.16 Reset
The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input
with an internal pull-up, a bidirectional reset input/output (open drain output with an
internal pull-up), or as push-pull reset output. These modes are selected by the RPE
(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.
Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and
this pin always functions as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this pin will function as dened by the RPE and RPE1
bits. Only a power-up reset will temporarily override the selection dened by RPE and
RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.
Remark: During a power cycle, VDD must fall below VPOR before power is reapplied, in
order to ensure a power-on reset (see Table 11 “Static characteristics” on page 51).
Remark: When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specied level. When system power is removed VDD
will fall below the minimum specied operating voltage. When using an oscillator
frequency above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when VDD falls below the minimum specied
operating voltage.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user congured via UCFG1, UCGF2);
Power-on detect;
Brownout detect;
Watchdog timer;
Software reset;
UART break character detect reset.
For every reset source, there is a ag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These ag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one ag bit may be set:
During a power-on reset, both POF and BOF are set but the other ag bits are
cleared.
For any other reset, previously set ag bits that have not been cleared will remain set.
Table 8.
Reset pin modes
P1.5/RST mode
RPE1 (UCFG2.0) RPE (UCFG1.6)
General purpose input
0
Reset input with pull-up
0
1
Bidirectional reset input/output (open drain with pull-up)
1
0
Reset output
1
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| P89LPC954FBD44-S | 功能描述:8位微控制器 -MCU 16K FL/1K RAM/512B EE/10B ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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