参数资料
型号: P89LPC954FBD44,151
厂商: NXP Semiconductors
文件页数: 29/69页
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
标准包装: 160
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 40
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
35 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
stop bit is not saved. The baud rate is programmable to either 1
16 or
1
32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer
1 output rate available to both UARTs.
7.19.4 Mode 3
11 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8
data bits (LSB rst), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overow rate or the Baud Rate Generator (described in
7.19.5 Baud rate generator and selection
Each enhanced UART has an independent Baud Rate Generator. The baud rate is
determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UARTs can use either Timer 1 or their respective baud rate generator output (see
Figure 8). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared.
The independent Baud Rate Generators use OSCCLK.
7.19.6 Framing error
Framing error is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6)
is ‘1’, framing errors can be made available in SnCON.7 respectively. If SMOD0 is ‘0’,
SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up
when SMOD0 is ‘0’.
7.19.7 Break detect
Break detect is reported in the status register (SnSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
7.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the rst character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Fig 8.
Baud rate sources for UART (Modes 1, 3)
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa897
÷2
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