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参数资料
| 型号： | P89LPC954FBD44,151 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 30/69页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 16K 44LQFP |
| 标准包装： | 160 |
| 系列： | LPC900 |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 18MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 40 |
| 程序存储器容量： | 16KB（16K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 512 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.4 V ~ 3.6 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LQFP |
| 包装： | 托盘 |
| 配用： | 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X |
| 其它名称： | 568-7917 568-7917-ND 568-8269 935284303151 P89LPC954FBD44,151-ND P89LPC954FBD44-S P89LPC954FBD44-S-ND |
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P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
36 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Double buffering can be disabled. If disabled (DBMOD_n, i.e., SnSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD_n = 0).
7.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI_n interrupt is generated
when the double buffer is ready to receive new data.
7.19.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8_n can be written before or after SnBUF is written, as
long as TB8_n is updated some time before that bit is shifted out. TB8_n must not be
changed until the bit is shifted out, as indicated by the TI_n interrupt.
If double buffering is enabled, TB8_n must be updated before SnBUF is written, as TB8_n
will be double-buffered together with SnBUF data.
7.20 I2C-bus serial interface
I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected
to the bus, and it has the following features:
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I2C-bus may be used for test and diagnostic purposes.
a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
Fig 9.
I2C-bus conguration
OTHER DEVICE
WITH I2C-BUS
INTERFACE
SDA
SCL
RPU
OTHER DEVICE
WITH I2C-BUS
INTERFACE
P1.3/SDA
P1.2/SCL
I2C MCU
I2C-bus
002aab410
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89LPC954FBD44-S | 功能描述:8位微控制器 -MCU 16K FL/1K RAM/512B EE/10B ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC954FBD48 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC |
| P89LPC954FBD48,151 | 功能描述:8位微控制器 -MCU 8B MCU 2-CLOCK 80C51 8/16KB 3V 10B RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89LPC970 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash |
| P89LPC970FDH | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB wide-voltage byte-erasable flash |
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