参数资料
型号: P89LPC954FBD44,151
厂商: NXP Semiconductors
文件页数: 49/69页
文件大小: 0K
描述: IC 80C51 MCU FLASH 16K 44LQFP
标准包装: 160
系列: LPC900
核心处理器: 8051
芯体尺寸: 8-位
速度: 18MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 40
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 2.4 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-LQFP
包装: 托盘
配用: 568-1759-ND - EMULATOR DEBUGGER/PROGRMMR LPC9X
其它名称: 568-7917
568-7917-ND
568-8269
935284303151
P89LPC954FBD44,151-ND
P89LPC954FBD44-S
P89LPC954FBD44-S-ND
P89LPC952_954_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 24 July 2008
53 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
11. Dynamic characteristics
Table 12.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specied.
Tamb = 40 °C to +85 °C for industrial applications, unless otherwise specied.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc = 12 MHz
Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to
± 1 % at
Tamb =25 °C; clock
doubler option = OFF
(default)
7.189
7.557
7.189
7.557
MHz
nominal f = 14.7456 MHz;
clock doubler option = ON,
VDD = 2.7 V to 3.6 V
14.378
15.114
14.378 15.114 MHz
fosc(WD)
internal watchdog
oscillator frequency
320
520
320
520
kHz
fosc
oscillator frequency
0
12
-
MHz
Tcy(clk)
clock cycle time
83
-
ns
fCLKLP
low-power select clock
frequency
0
8
-
MHz
Glitch lter
tgr
glitch rejection time
P1.5/RST pin
-
50
-
50
ns
any pin except P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
33
Tcy(clk) tCLCX
33
-
ns
tCLCX
clock LOW time
33
Tcy(clk) tCHCX
33
-
ns
tCLCH
clock rise time
-8
-
8
ns
tCHCL
clock fall time
-8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle
time
16Tcy(clk)
-
1333
-
ns
tQVXH
output data set-up to
clock rising edge time
13Tcy(clk)
-
1083
-
ns
tXHQX
output data hold after
clock rising edge time
-Tcy(clk) + 20
-
103
ns
tXHDX
input data hold after
clock rising edge time
-0
-
0
ns
tXHDV
input data valid to clock
rising edge time
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK
6
0
2.0
MHz
master
-
CCLK
4
-
3.0
MHz
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