2004 Microchip Technology Inc.
DS30491C-page 17
PIC18F6585/8585/6680/8680
PORTE is a bidirectional I/O port.
RE0/RD/AD8
RE0
RD(6)
AD8(3)
211
4
I/O
I
I/O
ST
TTL
Digital I/O.
Read control for Parallel Slave Port
(see WR and CS pins).
External memory address/data 8.
RE1/WR/AD9
RE1
WR(6)
AD9(3)
110
3
I/O
I
I/O
ST
TTL
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
External memory address/data 9.
RE2/CS/AD10
RE2
CS(6)
AD10(3)
64
9
78
I/O
I
I/O
ST
TTL
Digital I/O.
Chip select control for Parallel Slave
Port (see RD and WR).
External memory address/data 10.
RE3/AD11
RE3
AD11(3)
63
8
77
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
RE4/AD12
RE4
AD12(3)
62
7
76
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
RE5/AD13/P1C
RE5
AD13(3)
P1C(7)
61
6
75
I/O
ST
TTL
ST
Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.
RE6/AD14/P1B
RE6
AD14(3)
P1B(7)
60
5
74
I/O
ST
TTL
ST
Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.
RE7/CCP2/AD15
RE7
CCP2(1,4)
AD15(3)
59
4
73
I/O
ST
TTL
Digital I/O.
Capture 2 input/Compare 2 output/
PWM 2 output.
External memory address/data 15.
TABLE 1-2:
PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PIC18F6X8X PIC18F8X8X
TQFP PLCC
TQFP
Legend: TTL
= TTL compatible input
CMOS
= CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1:
Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.
2:
Default assignment when CCP2MX is set.
3:
External memory interface functions are only available on PIC18F8X8X devices.
4:
CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is
multiplexed with either RB3 or RC1.
5:
PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
6:
PSP is available in Microcontroller mode only.
7:
On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX
configuration bit.