2004 Microchip Technology Inc.
DS30491C-page 253
PIC18F6585/8585/6680/8680
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1.
Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion:
Set GO/DONE bit (ADCON0 register)
5.
Wait for A/D conversion to complete by either:
Polling for the GO/DONE bit to be cleared
or
Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF if required.
7.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 19-2:
ANALOG INPUT MODEL
VAIN
CPIN
Rs
ANx
5 pF
VDD
VT = 0.6V
ILEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD = 120 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
(k
)
VDD
± 500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
= sampling switch resistance
RSS