PIC18F6585/8585/6680/8680
DS30491C-page 170
2004 Microchip Technology Inc.
15.2.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCPxIE (PIE registers) clear to avoid false interrupts
and should clear the flag bit, CCPxIF, following any
such change in operating mode.
15.2.4
CCP PRESCALER
There are four prescaler settings specified by bits
CCPxM3:CCPxM0. Whenever the CCPx module is
turned off, or the CCPx module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. The prescaler counter will not be
cleared; therefore, the first capture may be from a
non-zero
prescaler.
shows
the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.2.5
CAN MESSAGE TIME-STAMP
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to time-stamp the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 15-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
CLRF
CCP1CON
; Turn CCP module off
MOVLW
NEW_CAPT_PS
; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with
; this value
CCPR1H
CCPR1L
TMR1H
TMR1L
Set Flag bit CCP1IF
TMR3
Enable
Q’s
CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
CCPR2H
CCPR2L
TMR1H
TMR1L
Set Flag bit CCP2IF
TMR3
Enable
Q’s
CCP2CON<3:0>
CCP2 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR3H
TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1