PIC18F6585/8585/6680/8680
DS30491C-page 70
2004 Microchip Technology Inc.
PORTJ(3)
Read PORTJ pins, Write PORTJ Data Latch
xxxx xxxx
PORTH(3)
Read PORTH pins, Write PORTH Data Latch
xxxx xxxx
PORTG
—
—RG5(6)
Read PORTG pins, Write PORTG Data Latch
--0x xxxx
PORTF
Read PORTF pins, Write PORTF Data Latch
xxxx xxxx
PORTE
Read PORTE pins, Write PORTE Data Latch
xxxx xxxx
PORTD
Read PORTD pins, Write PORTD Data Latch
xxxx xxxx
PORTC
Read PORTC pins, Write PORTC Data Latch
xxxx xxxx
PORTB
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
PORTA
—RA6(1)
Read PORTA pins, Write PORTA Data Latch(1)
-x0x 0000
SPBRGH
Enhanced USART Baud Rate Generator High Byte
0000 0000
BAUDCON
—
RCIDL
—
SCKP
BRG16
—
WUE
ABDEN
-1-0 0-00
ECCP1DEL
PRSEN
PDC6
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
0000 0000
TXERRCNT
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
0000 0000
RXERRCNT
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
0000 0000
COMSTAT
Mode 0
RXB0OVFL
RXB1OVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
0000 0000
COMSTAT
Mode 1
—
RXBnOVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
-000 0000
COMSTAT
Mode 2
FIFOEMPTY RXBnOVFL
TXBO
TXBP
RXBP
TXWARN
RXWARN
EWARN
0000 0000
CIOCON
TX2SRC
TX2EN
ENDRHI
CANCAP
—
0000 ----
BRGCON3
WAKDIS
WAKFIL
—
SEG2PH2
SEG2PH1 SEG2PH0 00-- -000
BRGCON2
SEG2PHT
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000 0000
BRGCON1
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000 0000
CANCON
Mode 0
REQOP2
REQOP1
REQOP0
ABAT
WIN2
WIN1
WIN0
—
1000 000-
CANCON
Mode 1
REQOP2
REQOP1
REQOP0
ABAT
—
1000 ----
CANCON
Mode 2
REQOP2
REQOP1
REQOP0
ABAT
FP3
FP2
FP1
FP0
1000 0000
CANSTAT
Mode 0
OPMODE2
OPMODE1
OPMODE0
—
ICODE2
ICODE1
ICODE0
—
000- 0000
CANSTAT
Modes 0, 1
OPMODE2
OPMODE1
OPMODE0
EICODE4
EICODE3
EICODE2
EICODE1
EICODE0
0000 0000
ECANCON
MDSEL1
MDSEL0
FIFOWM
EWIN4
EWIN3
EWIN2
EWIN1
EWIN0
0001 0000
RXB0D7
RXB0D77
RXB0D76
RXB0D75
RXB0D74
RXB0D73
RXB0D72
RXB0D71
RXB0D70
xxxx xxxx
RXB0D6
RXB0D67
RXB0D66
RXB0D65
RXB0D64
RXB0D63
RXB0D62
RXB0D61
RXB0D60
xxxx xxxx
RXB0D5
RXB0D57
RXB0D56
RXB0D55
RXB0D54
RXB0D53
RXB0D52
RXB0D51
RXB0D50
xxxx xxxx
RXB0D4
RXB0D47
RXB0D46
RXB0D45
RXB0D44
RXB0D43
RXB0D42
RXB0D41
RXB0D40
xxxx xxxx
RXB0D3
RXB0D37
RXB0D36
RXB0D35
RXB0D34
RXB0D33
RXB0D32
RXB0D31
RXB0D30
xxxx xxxx
RXB0D2
RXB0D27
RXB0D26
RXB0D25
RXB0D24
RXB0D23
RXB0D22
RXB0D21
RXB0D20
xxxx xxxx
RXB0D1
RXB0D17
RXB0D16
RXB0D15
RXB0D14
RXB0D13
RXB0D12
RXB0D11
RXB0D10
xxxx xxxx
RXB0D0
RXB0D07
RXB0D06
RXB0D05
RXB0D04
RXB0D03
RXB0D02
RXB0D01
RXB0D00
xxxx xxxx
TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
Legend:
x
= unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note
1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator
modes.
2:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
3:
These registers are unused on PIC18F6X80 devices; always maintain these clear.
4:
These bits have multiple functions depending on the CAN module mode selection.
5:
Meaning of this register depends on whether this buffer is configured as transmit or receive.
6:
RG5 is available as an input when MCLR is disabled.
7:
This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2.