2004 Microchip Technology Inc.
DS30491C-page 173
PIC18F6585/8585/6680/8680
15.4
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. For
PWM mode to function properly, the TRIS bit for the
CCPx pin must be cleared to make it an output.
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
FIGURE 15-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4:
PWM OUTPUT
15.4.1
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
The PWM duty cycle is latched from CCPR1L into
CCPR1H
15.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contain the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
EQUATION 15-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.
Note:
Clearing the CCPxCON register will force
the CCPx PWM output latch to the default
low level. This is not the port data latch.
CCPRxL (Master)
CCPRxH (Slave)
Comparator
TMR2
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCPxCON<5:4>
Clear Timer,
set CCPx pin and
latch D.C.
TRIS bit
CCPx
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or
2 bits of the prescaler to create 10-bit time base.
Comparator
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note:
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] 4 TOSC
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPRxL:CCPxCON<5:4>)
TOSC (TMR2 Prescale Value)