PIC18F6585/8585/6680/8680
DS30491C-page 266
2004 Microchip Technology Inc.
FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
21.2
Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
21.3
Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
21.4
Effects of a Reset
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON<6>) and selects the high-
voltage range by clearing bit CVRR (CVRCON<5>).
The VRSS value select bits, CVRCON<3:0>, are also
cleared.
21.5
Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin with an
input signal present will increase current consumption.
Connecting RF5 as a digital output with VRSS enabled
will also increase current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence
output
for
external
connections
to
VREF.
CVRR
8R
CVR3
CVR0
(From CVRCON<3:0>)
16-1 Analog Mux
8R
R
CVREN
CVREF
16 Stages
CVRSS = 0
VDD VREF+
CVRSS = 0
CVRSS = 1
VREF-
CVRSS = 1