2004 Microchip Technology Inc.
DS30491C-page 57
PIC18F6585/8585/6680/8680
4.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
4.7
Instructions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte (LSB) of an
instruction word is always stored in a program memory
location with an even address (LSB = 0).
Figure 4-6shows an example of how instruction words are stored
in the program memory. To maintain alignment with
instruction boundaries, the PC increments in steps of 2
The CALL and GOTO instructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>
which accesses the desired byte address in program
memory. Instruction #2 in
Figure 4-6 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions which encode a
relative address offset operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single-word instructions that the
Summary” provides further details of the instruction
set.
FIGURE 4-6:
INSTRUCTIONS IN PROGRAM MEMORY
All instructions are single cycle except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2
Execute 2
3. BRA
SUB_1
Fetch 3
Execute 3
4. BSF
PORTA, 3 (Forced NOP)
Fetch 4
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
Word Address
LSB = 1
LSB = 0
↓
Program Memory
Byte Locations
→
000000h
000002h
000004h
000006h
Instruction 1:
MOVLW
055h
0Fh
55h
000008h
Instruction 2:
GOTO
000006h
0EFh
03h
00000Ah
0F0h
00h
00000Ch
Instruction 3:
MOVFF
123h, 456h
0C1h
23h
00000Eh
0F4h
56h
000010h
000012h
000014h