参数资料
型号: PI7C9X20404GPBNBE
厂商: Pericom
文件页数: 13/79页
文件大小: 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 189
系列: GreenPacket™
应用: 封装开关,4 端口/4 线道
接口: PCI Express
封装/外壳: 148-LFBGA
供应商设备封装: 148-LFBGA(12x12)
包装: 托盘
安装类型: 表面贴装
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 20 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
5.6.5 CPLD
CPLD queue is used for storing completion data. If the received TLP is of the completion type and is determined to
have payload coming with the header, the payload data would be put into CPLD queue. There are two CPLD queues
for VC0 and VC1 respectively.
5.7
TRANSACTION ORDERING
Within a VPPB, a set of ordering rules is defined to regulate the transactions on the PCI Express Switch including
Memory, IO, Configuration and Messages, in order to avoid deadlocks and to support the Producer-Consumer
model. The ordering rules defined in table 5-4 apply within a single Traffic Class (TC). There is no ordering
requirement among transactions within different TC labels. Since the transactions with the same TC label are not
allowed to map into different virtual channels, it implies no ordering relationship between the traffic in VC0 and
VC1.
Table 5-4 Summary of PCI Express Ordering Rules
Row Pass Column
Posted
Request
Read
Request
Non-posted Write
Request
Read
Completion
Non-posted Write
Completion
Posted Request
Yes/No1
Yes5
Read Request
No2
Yes
Non-posted Write Request
No2
Yes
Read Completion
Yes/No3
Yes
Non-Posted Write
Completion
Yes4
Yes
1. When the Relaxed Ordering Attribute bit is cleared, the Posted Request transactions including memory write and
message request must complete on the egress bus of VPPB in the order in which they are received on the ingress
bus of VPPB. If the Relaxed Ordering Attribute bit is set, the Posted Request is permitted to pass over other Posted
Requests occurring before it.
2. A Read Request transmitting in the same direction as a previously queued Posted Request transaction must push
the posted write data ahead of it. The Posted Request transaction must complete on the egress bus before the Read
Request can be attempted on the egress bus. The Read transaction can go to the same location as the Posted data.
Therefore, if the Read transaction were to pass the Posted transaction, it would return stale data.
3. When the Relaxed Ordering Attribute bit is cleared, a Read completion must ‘‘pull’’ ahead of previously queued
posted data transmitting in the same direction. In this case, the read data transmits in the same direction as the
posted data, and the requestor of the read transaction is on the same side of the VPPB as the completer of the posted
transaction. The posted transaction must deliver to the completer before the read data is returned to the requestor. If
the Relaxed Ordering Attribute bit is set, then a read completion is permitted to pass a previously queued Memory
Write or Message Request.
4. Non-Posted Write Completions are permitted to pass a previous Memory Write or Message Request transaction.
Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship.
5. Posted Request transactions must be given opportunities to pass Non-posted Read and Write Requests as well as
Completions. Otherwise, deadlocks may occur when some older Bridges that do not support delayed transactions
are mixed with PCIe Switch in the same system. A fairness algorithm is used to arbitrate between the Posted Write
queue and the Non-posted transaction queue.
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