参数资料
| 型号： | PI7C9X20404GPBNBE |
| 厂商： | Pericom |
| 文件页数： | 29/79页 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 产品变化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 标准包装： | 189 |
| 系列： | GreenPacket™ |
| 应用： | 封装开关，4 端口/4 线道 |
| 接口： | PCI Express |
| 封装/外壳： | 148-LFBGA |
| 供应商设备封装： | 148-LFBGA（12x12） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 35 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
DESCRIPTION
31:24
Secondary Latency
Timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
7:4
I/O Base Address
[15:12]
RW
Defines the bottom address of the I/O address range for the Bridge to
determine when to forward I/O transactions from one interface to the other.
The upper 4 bits correspond to address bits [15:12] and are writable. The
lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The
upper 16 bits corresponding to address bits [31:16] are defined in the I/O base
address upper 16 bits address register.
Reset to 0h.
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
11:8
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
15:12
I/O Limit Address
[15:12]
RW
Defines the top address of the I/O address range for the Bridge to determine
when to forward I/O transactions from one interface to the other. The upper 4
bits correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16
bits corresponding to address bits [31:16] are defined in the I/O limit address
upper 16 bits address register.
Reset to 0h.
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
20:16
Reserved
RO
Reset to 00000b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the secondary side of the port in a Switch.
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
26:25
DEVSEL_L timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RO
Set to 1 (by a completer) whenever completing a request in the secondary side
using Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status in the secondary side.
Reset to 0b.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外围驱动器与原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C9X20404SLCFDEX | 功能描述:外围驱动器与原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C9X20505GPBNDE | 功能描述:外围驱动器与原件 - PCI 5port 5lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
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