参数资料
型号: PI7C9X20404GPBNBE
厂商: Pericom
文件页数: 32/79页
文件大小: 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 189
系列: GreenPacket™
应用: 封装开关,4 端口/4 线道
接口: PCI Express
封装/外壳: 148-LFBGA
供应商设备封装: 148-LFBGA(12x12)
包装: 托盘
安装类型: 表面贴装
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 38 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
Reset to 80h.
7.2.26
INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Line
RW
Reset to 00h.
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Interrupt Pin
RO
The Switch implements INTA virtual wire interrupt signals to represent hot-
plug events at downstream ports. The default value on the downstream ports
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
Parity Error
Response
RW
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
17
S_SERR# enable
RW
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
Reset to 0b.
18
ISA Enable
RW
0b: Forwards downstream all I/O addresses in the address range defined by
the I/O Base, I/O Base, and Limit registers
1b: Forwards upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
Reset to 0b.
19
VGA Enable
RW
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
20
VGA 16-bit decode
RW
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3.
21
Master Abort Mode
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Secondary Bus Reset
RW
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
Reset to 0b.
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