参数资料
| 型号： | PI7C9X20404GPBNBE |
| 厂商： | Pericom |
| 文件页数： | 15/79页 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 产品变化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 标准包装： | 189 |
| 系列： | GreenPacket™ |
| 应用： | 封装开关，4 端口/4 线道 |
| 接口： | PCI Express |
| 封装/外壳： | 148-LFBGA |
| 供应商设备封装： | 148-LFBGA（12x12） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 22 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
6 EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS
The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bi-directional
serial data). The Switch may control an ISSI IS24C04 or compatible parts using into 512x8 bits. The EEPROM is
used to initialize a number of registers before enumeration. This is accomplished after PRST# is de-asserted, at
which time the data from the EEPROM is loaded. The EEPROM interface is organized into a 16-bit base, and the
Switch supplies a 7-bit EEPROM word address. The Switch does not control the EEPROM address input. It can
only access the EEPROM with address input set to 0.
The System Management Bus interface consists of two pins: SMBCLK (System Management Bus Clock input) and
SMBDATA (System Management Bus Data input/ output).
6.1
EEPROM INTERFACE
6.1.1 AUTO MODE EERPOM ACCESS
The Switch may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer.
The EEPROM start-control, address, and read/write commands can be accessed through the configuration register.
Before each access, the software should check the Autoload Status bit before issuing the next start.
6.1.2 EEPROM MODE AT RESET
During a reset, the Switch will automatically load the information/data from the EEPROM if the automatic load
condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload
initiates right after the reset.
During the autoload, the Bridge will read sequential words from the EEPROM and write to the appropriate registers.
Before the Bridge registers can be accessed through the host, the autoload condition should be verified by reading
bit [3] offset DCh (EEPROM Autoload Status). The host access is allowed only after the status of this bit is set to '0'
which indicates that the autoload initialization sequence is complete.
6.1.3 EEPROM SPACE ADDRESS MAP
15 – 8
7 – 0
BYTE OFFSET
EEPROM Signature (1516h)
00h
Vendor ID
02h
Device ID
04h
Extended VC Count / Link Capability / Switch Mode Operation / Interrupt pin for Port 1 ~ 3
06h
Subsystem Vender ID
08h
Subsystem ID
0Ah
Max_Payload_Size Support / ASPM Support / Role_Base Error Reporting / RefClk ppm
Difference
0Ch
Reserved
0Eh
PM Data for Port 0
PM Capability for Port 0
10h
PM Data for Port 1
PM Capability for Port 1
12h
PM Data for Port 2
PM Capability for Port 2
14h
PM Data for Port 3
PM Capability for Port 3
16h
Reserved
18h
Reserved
1Ah
Reserved
1Ch
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