参数资料
型号: PI7C9X20404GPBNBE
厂商: Pericom
文件页数: 47/79页
文件大小: 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 189
系列: GreenPacket™
应用: 封装开关,4 端口/4 线道
接口: PCI Express
封装/外壳: 148-LFBGA
供应商设备封装: 148-LFBGA(12x12)
包装: 托盘
安装类型: 表面贴装
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 51 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
14:12
Max_Read_
Request_Size
RO
This field sets the maximum Read Request size for the device as a Requester.
Since the Switch does not generate read request by itself, these bits are
hardwired to 000b.
Reset to 000b.
15
Reserved
RO
Reset to 0b.
7.2.67
DEVICE STATUS REGISTER – OFFSET E8h
BIT
FUNCTION
TYPE
DESCRIPTION
16
Correctable Error
Detected
RW1C
Asserted when correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Reset to 0b.
17
Non-Fatal Error
Detected
RW1C
Asserted when non-fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Reset to 0b.
18
Fatal Error Detected
RW1C
Asserted when fatal error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register.
Reset to 0b.
19
Unsupported Request
Detected
RW1C
Asserted when unsupported request is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register.
Reset to 0b.
20
AUX Power
Detected
RO
Asserted when the AUX power is detected by the Switch
Reset to 1b.
21
Transactions Pending
RO
Each port of Switch does not issue Non-posted Requests on its own behalf, so
this bit is hardwired to 0b.
Reset to 0b.
31:22
Reserved
RO
Reset to 0.
7.2.68
LINK CAPABILITIES REGISTER – OFFSET ECh
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
Maximum Link
Speed
RO
Read as 0001b to indicate the maximum speed of the Express link is 2.5 Gb/s.
9:4
Maximum Link
Width
RO
Indicates the maximum width of the given PCIe Link. The width of each port
is determined by strapped pin or EEPROM pre-loaded value.
Reset to 000001b (x1) for Port 0.
Reset to 000001b (x1) for Port 1.
Reset to 000001b (x1) for Port 2.
Reset to 000001b (x1) for Port 3.
11:10
Active State Power
Management
(ASPM) Support
RO
Indicates the level of ASPM supported on the given PCIe Link. Each port of
Switch supports L0s and L1 entry. The default value may be changed by
SMBus or auto-loading from EEPROM.
Reset to 01b.
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