参数资料
型号: PI7C9X20404GPBNBE
厂商: Pericom
文件页数: 28/79页
文件大小: 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 189
系列: GreenPacket™
应用: 封装开关,4 端口/4 线道
接口: PCI Express
封装/外壳: 148-LFBGA
供应商设备封装: 148-LFBGA(12x12)
包装: 托盘
安装类型: 表面贴装
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 34 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Cache Line Size
RW
The cache line size register is set by the system firmware and the operating
system cache line size. This field is implemented by PCI Express devices as a
RW field for legacy compatibility, but it has no impact on any PCI Express
device functionality.
Reset to 0b.
7.2.8
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Primary Latency
timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
7.2.9
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
23:16
Header Type
RO
Read as 01h to indicate that the register layout conforms to the standard PCI-
to-PCI Bridge layout.
7.2.10
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Primary Bus Number
RW
Indicates the number of the PCI bus to which the primary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.11
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Secondary Bus
Number
RW
Indicates the number of the PCI bus to which the secondary interface is
connected. The value is set in software during configuration.
Reset to 00h.
7.2.12
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
DESCRIPTION
23:16
Subordinate Bus
Number
RW
Indicates the number of the PCI bus with the highest number that is
subordinate to the Bridge. The value is set in software during configuration.
Reset to 00h.
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