参数资料
型号: PI7C9X20404GPBNBE
厂商: Pericom
文件页数: 59/79页
文件大小: 0K
描述: IC PCIE PACKET SWITCH 148LFBGA
产品变化通告: Product Discontinuation Notice 22/Jan/2010
标准包装: 189
系列: GreenPacket™
应用: 封装开关,4 端口/4 线道
接口: PCI Express
封装/外壳: 148-LFBGA
供应商设备封装: 148-LFBGA(12x12)
包装: 托盘
安装类型: 表面贴装
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 62 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
3:1
VC Arbitration
Select
RW
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Switch are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
15:4
Reserved
RO
Reset to 0.
7.2.90
PORT VC STATUS REGISTER – OFFSET 14Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
VC Arbitration Table
Status
RO
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
Reset to 0b.
31:17
Reserved
RO
Reset to 0.
7.2.91
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Port Arbitration
Capability
RO
It indicates the types of Port Arbitration supported by the VC resource. The
Switch supports Hardware fixed arbitration scheme, e.g., Round Robin,
Weight Round Robin (WRR) arbitration with 128 phases (3~4 enabled ports)
and Time-based WRR with 128 phases (3~4 enabled ports). Note that the
Time-based WRR is only valid in VC1.
Reset to 00001001b.
13:8
Reserved
RO
Reset to 000000b.
14
Advanced Packet
Switching
RO
When set, it indicates the VC resource only supports transaction optimized
for Advanced Packet Switching (AS).
Reset to 0b.
15
Reject Snoop
Transactions
RO
This bit is not applied to PCIe Switch.
Reset to 0b.
22:16
Maximum Time
Slots
RO
It indicates the maximum numbers of time slots (minus one) are allocated for
Isochronous traffic. The default value may be changed by SMBus or auto-
loading from EEPROM.
Reset to 7Fh.
23
Reserved
RO
Reset to 0b.
31:24
Port Arbitration
Table Offset
RO
It indicates the location of the Port Arbitration Table (n) as an offset from the
base address of the Virtual Channel Capability register in the unit of DQWD
(16 bytes).
Reset to 04h for Port Arbitration Table (0).
7.2.92
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
TC/VC Map
RW
This field indicates the TCs that are mapped to the VC resource. Bit locations
within this field correspond to TC values. When the bits in this field are set, it
means that the corresponding TCs are mapped to the VC resource. The
default value may be changed by SMBus or auto-loading from EEPROM.
Reset to FFh.
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