参数资料
| 型号： | PI7C9X20404GPBNBE |
| 厂商： | Pericom |
| 文件页数： | 45/79页 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 产品变化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 标准包装： | 189 |
| 系列： | GreenPacket™ |
| 应用： | 封装开关，4 端口/4 线道 |
| 接口： | PCI Express |
| 封装/外壳： | 148-LFBGA |
| 供应商设备封装： | 148-LFBGA（12x12） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 5 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
3.2
PORT CONFIGURATION SIGNALS .......................................................................................................12
3.3
HOT PLUG SIGNALS ...............................................................................................................................13
3.4
MISCELLANEOUS SIGNALS..................................................................................................................13
3.5
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................14
3.6
POWER PINS.............................................................................................................................................14
4
PIN ASSIGNMENTS .........................................................................................................................................15
4.1
PIN LIST OF 148-PIN LFBGA....................................................................................................................15
5
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH ....................................................................................................................................................... 19
5.6.2
PD ....................................................................................................................................................... 19
5.6.3
NPHD ................................................................................................................................................. 19
5.6.4
CPLH .................................................................................................................................................. 19
5.6.5
CPLD .................................................................................................................................................. 20
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................21
5.9
VC ARBITRATION ...................................................................................................................................21
5.10
FLOW CONTROL .....................................................................................................................................21
5.11
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 22
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 22
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 24
6.2
SMBUS INTERFACE .................................................................................................................................29
7
REGISTER DESCRIPTION .............................................................................................................................30
7.1
REGISTER TYPES ....................................................................................................................................30
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS....................................................................30
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 32
7.2.2
DEVICE ID REGISTER – OFFSET 00h............................................................................................. 32
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 32
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 33
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 33
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