参数资料
| 型号： | PI7C9X20404GPBNBE |
| 厂商： | Pericom |
| 文件页数： | 33/79页 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 产品变化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 标准包装： | 189 |
| 系列： | GreenPacket™ |
| 应用： | 封装开关，4 端口/4 线道 |
| 接口： | PCI Express |
| 封装/外壳： | 148-LFBGA |
| 供应商设备封装： | 148-LFBGA（12x12） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 39 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
23
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Primary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
25
Secondary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
26
Master Timeout
Status
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Discard Timer
SERR# enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
31:28
Reserved
RO
Reset to 0h.
7.2.29
POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Enhanced
Capabilities ID
RO
Read as 01h to indicate that these are power management enhanced capability
registers.
7.2.30
NEXT ITEM POINTER REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
At upstream ports, the pointer points to the Vital Protocol Data (VPD)
capability register (9Ch).
At downstream ports, the pointer points to the Message capability register
(8Ch).
Reset to 9Ch (Upstream port).
Reset to 8Ch (Downstream port).
7.2.31
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Power Management
Revision
RO
Read as 011b to indicate the device is compliant to Revision 1.2 of PCI
Power Management Interface Specifications.
19
PME# Clock
RO
Does not apply to PCI Express. Must be hardwired to 0b.
20
Reserved
RO
Reset to 0b.
21
Device Specific
Initialization
RO
Read as 0b to indicate Switch does not have device specific initialization
requirements. The default value may be changed by SMBus or auto-loading
from EEPROM.
24:22
AUX Current
RO
Reset as 111b to indicate the Switch needs 375 mA in D3 state. The default
value may be changed by SMBus or auto-loading from EEPROM.
25
D1 Power State
Support
RO
Read as 1b to indicate Switch supports the D1 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
26
D2 Power State
Support
RO
Read as 1b to indicate Switch supports the D2 power management state. The
default value may be changed by SMBus or auto-loading from EEPROM.
31:27
PME# Support
RO
Read as 11111b to indicate Switch supports the forwarding of PME# message
in all power states. The default value may be changed by SMBus or auto-
loading from EEPROM.
7.2.32
POWER MANAGEMENT DATA REGISTER – OFFSET 84h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Power State
RW
Indicates the current power state of the Switch. Writing a value of D0 when
the previous state was D3 cause a hot reset without asserting DWNRST_L.
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