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参数资料
| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 10/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
18
xmt1_fifo_prog_full_flag
I
Active High. Transmit FIFO1 contains a number of entries greater than or equal to
the threshold set in register 0x68, bits 61:56.
Miscellaneous Interface Signals
SPCI_done
I
Active High. Single PCI Access done.
Control Bus Interface Signals
cntl_data_in[63:0]
I
Active High. A 64-bit bus used to read to the various memory mapped registers of
the QL5064.
cntl_wrt_nrd
O
Control bus write/not read. When ‘1’ current access to the control bus is a write.
When ‘0’ current access to the control bus is a read.
cntl_addr[7:3]
O
Active High. Control bus address bits 7:3. Selects which of the 64-bit registers the
control bus is accessing.
cntl_be[7:0]
O
cntl_be[7]
cntl_data[63:56]
cntl_be[6]
cntl_data[55:48]
cntl_be[5]
cntl_data[47:40]
cntl_be[4]
cntl_data[39:32]
cntl_be[3]
cntl_data[31:24]
cntl_be[2]
cntl_data[23:16]
cntl_be[1]
cntl_data[15:08]
cntl_be[0]
cntl_data[07:00]
cntl_data_out[63:0]
O
Active High. A 64-bit bus used to write to the various QL5064 memory mapped
registers.
cntl_cs
O
Active High. Control bus chip select.
Data OUT Bus Interface Signals
data_out[63:0]
O
A 64-bit bus connecting to the FIFOs. Used by the FPGA to write data from the
FPGA to the PCI bus via the three output FIFOs.
data_outCS
O
Active High. Chip select for the data_out bus.
data_outDES[1:0]
O
Destination select for the data_out bus.
00 Transmit FIFO0
01 Transmit FIFO1
10 Target/Read Post FIFO
11 No destination (parked)
data_out_byte_sel[2:0]
O
Lane shifting selection for the construction registers before the FIFOs
data_out_BE[7:0] are also shifted accordingly. Sets the number of bytes to barrel
shift the 64-bit data_out bus and the 8-bit data_outBE bus.
data_outBE[7:0]
O
Active High. Indicates which byte lane is active for the current transfer occurring
on data_out[63:0].
data_outBE[7]
data_out[63:56]
data_outBE[6]
data_out[55:48]
data_outBE[5]
data_out[47:40]
data_outBE[4]
data_out[39:32]
data_outBE[3]
data_out[31:24]
data_outBE[2]
data_out[23:16]
data_outBE[1]
data_out[15:08]
data_outBE[0]
data_out[07:00]
Table 2: PCI Back-End Interface Signals (Continued)
Symbol
I/Oa
Description
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PDF描述 |
|---|---|
| QL5064-66APB456M | PCI BUS CONTROLLER, PBGA456 |
| QL5064-66APBN456C | PCI BUS CONTROLLER, PBGA456 |
| QL5064-66BPBN456M | PCI BUS CONTROLLER, PBGA456 |
| QL5064-75CPBN456I | PCI BUS CONTROLLER, PBGA456 |
| QL5064-75CPS484C | PCI BUS CONTROLLER, PBGA484 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5064-66APS484C-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66APS484I-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66BPS484C-5725 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484C-5616 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484I-5612 | 制造商:QuickLogic Corporation 功能描述: |
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