- 您现在的位置：买卖IC网 > PDF目录191942 > QL5064-33APB456M (QUICKLOGIC CORP) PCI BUS CONTROLLER, PBGA456 PDF资料下载
参数资料
| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 44/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页
2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
8
Internal Bus Structure
The internal interface between the PCI Controller and the FPGA logic cells is both simple and flexible. The
interface is configurable, based on the needs of the FPGA design. Configuration is accomplished at the time
of programming the FPGA.
The FPGA/PCI interface supports very high bandwidth data transfers via three 64-bit busses. The interface is
fully synchronous, and supports a separate clock from the PCI clock. The Interface clock can run at up to
100 MHz.
The interface has three busses: DataIN, DataOUT, and Control_DATA. The DataIN bus moves the data from
the PCI bus to the back-end. The DataOUT bus moves data from the back-end to the PCI bus. The
Control_DATA bus moves the data from the PCI bus to the back-end and from the back-end to the PCI bus.
It also accesses the internal control registers. All three busses can operate simultaneously at zero wait states.
Clocking
All bus accesses to the QL5064 from the FPGA (back-end) interface are synchronous to the back-end user
clock - called user_clk. The user_clk is supplied on a dedicated external pin. The PCI clock may be routed out
to a pin, and then back into the device to be used as the user_clk if desired. The user_clk signal may be
asynchronous to the pci_clk signal, and may run at up to 100 MHz with no PLL requirements.
All busses on the back-end of the QL5064 device can sustain data movement on every cycle of user_clk.
Figure 5: FPGA to PCI Synchronization
DataIN Bus Description
The DataIN bus transfers data from the PCI bus to the back-end interface. This data can come from three
different data paths: either one of the two DMA receive FIFOs, or the Target Write/Post FIFO. For proper
data management, empty and almost empty flags from the two DMA receive FIFOs are accessible to the back-
end design. The almost empty flags are configured through the Control_DATA bus interface or the PCI bus.
Interface to the Target Write/Post FIFO is accomplished through the Target interface signals. A block diagram
of the DataIN and Target control connections is shown in Figure 6.
Data is transferred to the DataIN bus in the same byte lane in which is was transferred over the PCI bus. To
assist with re-aligning or compacting data in the back-end interface, a byte-lane barrel shifter provides the
means to manipulate byte lane positioning. This is accomplished with the byte_select[2:0] input. See the
DataIN Bus section of the internal signal descriptions for more information.
PCI
FPGA
pci_clk
user_clk
PCI
FPGA
user_clk
or
osc
user_clk
相关PDF资料 |
PDF描述 |
|---|---|
| QL5064-66APB456M | PCI BUS CONTROLLER, PBGA456 |
| QL5064-66APBN456C | PCI BUS CONTROLLER, PBGA456 |
| QL5064-66BPBN456M | PCI BUS CONTROLLER, PBGA456 |
| QL5064-75CPBN456I | PCI BUS CONTROLLER, PBGA456 |
| QL5064-75CPS484C | PCI BUS CONTROLLER, PBGA484 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5064-66APS484C-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66APS484I-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66BPS484C-5725 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484C-5616 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484I-5612 | 制造商:QuickLogic Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。