2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
9
Figure 6: DataIN Bus Description
DataOUT Bus Description
The DataOUT bus is used to transfer data from the back-end interface to the PCI bus. This bus is connected
to three destinations within the QL5064 device: either one of the two DMA transmit FIFOs, or the Target
Read/Pre-Fetch FIFO. For proper data management and high data throughput, full and almost full flags are
available for each of the two DMA transmit FIFOs. The almost full flags are fully configurable via the
Control_DATA bus interface or the PCI bus. Interface to the Target Read/Pre-Fetch FIFO is accomplished
through the Target interface signals. A block diagram of the DataOUT connections is shown in Figure 7.
The data_outDES[1:0] signals select a particular FIFO to be connected to the DataOUT bus. A block diagram
of the DataOUT bus and its connections is shown in Figure 7.
Data written to the DMA transmit FIFOs or the Target Read/Pre-fetch FIFO must be set up in the same byte
lanes in which the data will be transferred in the PCI bus. To aid with aligning, re-aligning, or compacting data
that is to be written to the FIFOs via the DataOUT bus, a byte-lane barrel shifter is present, controlled by the
data_out_shift[2:0] signals. See the DataOUT bus section of Table 2 for more information.
pci cbe [7:0]
pci data
dataIN [63:0]
dataIN_bytesel [2:0]
rcv0_fifo_program_empty_flag
rcv0_fifo_ef
dataIN_BE[7:0]
dataIN_byteID [1:0]
rcv1_fifo_program_empty_flag
rcv1_fifo_ef
dataIN_src_sel[1:0]
dataIN_cs
user_clk
FPGA
Target/
Write
Post FIFO
(32 Deep)
DMA Rcv 1
or Target Write
Post FIFO
(64 Deep)
DMA Rcv 0
FIFO
(64 deep)
Chain Descriptor Tags
Byte lane [7:0]
Lane
Barrel
Shifter
Decode
0
1
2
3
0
1
2
0
1
2
3
64
8
64
8
64
8
64
3
8
2
DQ
PCI
Bus
PCI Core