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| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 15/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
22
Table 4: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
8
t
SWA
WA Setup Time to WCLK
1.0
t
HWA
WA Hold Time to WCLK
0.0
t
SWD
WD Setup Time to WCLK
1.0
t
HWD
WD Hold Time to WCLK
0.0
t
SWE
WE Setup Time to WCLK
1.0
t
HWE
WE Hold Time to WCLK
0.0
t
WCRD
WCLK to RD (WA=RA)a
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the
appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
5.0
5.3
5.6
5.9
7.1
Table 5: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. Stated timing for worst case Propagation Delay over process variation at V
CC = 3.3 V and TA = 25°C. Multiply by the
appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
1
2
3
4
8
tSRA
RA Setup Time to RCLK
1.0
tHRA
RA Hold Time to RCLK
0.0
tSRE
RE Setup Time to RCLK
1.0
tHRE
RE Hold Time to RCLK
0.0
tRCRD
RCLK to RDb]
b. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including
typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your
particular design.
4.0
4.3
4.6
4.9
6.1
Table 6: RAM Cell Asynchronous Read Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
8
RPDRD
RA to RDa
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of
your particular design.
3.0
3.3
3.6
3.9
5.1
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