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| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 16/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
23
Table 7: Input-Only Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of
your particular design.
1
2
3
4
8
12
24
t
IN
High Drive Input Delay
1.5
1.6
1.8
1.9
2.4
2.9
4.4
t
INI
High Drive Input, Inverting Delay
1.6
1.7
1.9
2.0
2.5
3.0
4.5
t
ISU
Input Register Set-Up Time
3.1
t
IH
Input Register Hold Time
0.0
t
lCLK
Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
t
lRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
t
lESU
Input Register Clock Enable Setup Time
2.3
t
lEH
Input Register Clock Enable Hold Time
0.0
Table 8: Clock Cells
Symbols
Parameter
Propagation Delays (ns)
Loads per Half Columna
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half
columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay.
The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
1
2
3
4
8
10
12
14
16
18
20
t
ACK
Array Clock Delay
1.2
1.3
1.5
.16
1.7
1.8
1.9
2
2.1
t
GCKP
Global Clock Pin Delay
0.7
t
GCKB
Global Clock Buffer Delay
0.8
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Table 9: I/O Cell Input Delays
Symbol
Parameter
Propagation Delays (ns) Fanouta
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the
appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
1
2
3
4
8
10
t
I/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
t
ISU
Input Register Set-Up Time
3.1
t
IH
Input Register Hold Time
0.0
t
lOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
t
lORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
t
lESU
Input Register Clock Enable Set-Up Time
2.3
tlEH
Input Register Clock Enable Hold Time
0.0
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