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参数资料
| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 43/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
7
Mailbox Registers and I
2O
The PCI interface contains 16 bytes of mailbox registers to support message/semaphore passing between the
programmable logic design and the PCI bus. These mailbox registers are memory mapped to a dedicated
register bank within the first 256 bytes of BAR 0. Eight bytes are provided for the FPGA to PCI direction, and
eight bytes are also provided for the PCI to FPGA direction. Status flags and interrupts are available for each
direction as well. Figure 4 shows the mailbox structure within the QL5064 device. Hardware controlled
queues allow full I
2O messaging support with a processor and local I2O drivers.
Figure 4: Mailbox Structure
full interrupt
empty interrupt
63
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
63
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
STATUS REGISTER
INTERRUPT CONTROL
interrupt
configuration
register
INTERRUPT CONTROL
8
empty interrupt
PCI BUS
CNTL
BUS
STATUS REGISTER
status
8
outgoing
decode
control
incoming
decode
control
status
full interrupt
mailbox 7
mailbox 5
mailbox 3
mailbox 1
PCI Outgoing Mailboxes
mailbox 6
mailbox 4
mailbox 2
mailbox 0
mailbox 7
mailbox 5
mailbox 3
mailbox 1
mailbox 6
mailbox 4
mailbox 2
mailbox 0
User Outgoing mailboxes
interrupt
configuration
register
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相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5064-66APS484C-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66APS484I-5541 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-66BPS484C-5725 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484C-5616 | 制造商:QuickLogic Corporation 功能描述: |
| QL5064-75CPS484I-5612 | 制造商:QuickLogic Corporation 功能描述: |
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