2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
5
Applications
The QL5064 device supports maximum PCI transfer rates, so many applications exist which are ideally suited
to the device's high performance. High speed data communications, telecommunications, and computing
systems are just a few of the broad range of applications areas that can benefit from the high speed PCI
interface and programmable logic.
The PCI Interface can also act as a PCI Host Controller. This can be accomplished by glue-less interface to
most popular 8/16/32/64-bit microprocessors.
Six FIFOs for Increased Performance
The PCI interface includes the following six FIFO buffers:
Two 64x64 PCI Master Transmit Buffers
Two 64x64 PCI Master Receive Buffers
One 16x64 PCI Target Read/Pre-Fetch Buffer
One 32x64 PCI Target Write/Post Buffer
All FIFO buffers are 72 bits wide (64 data bits + 8-bit byte enables). PCI Initiator-mode buffers are 64 deep
and support sustained burst transfers. PCI Target mode buffers are provided for both Read and Write
operations to the PCI Target, supporting pre-fetched reads with configurable registers.
All FIFOs can operate with independent read and write clocks, so that the programmable logic design can
interface to the FIFOs at up to 100 MHz (a clock asynchronous to the 33/66 MHz PCI clock). All data
synchronization is accomplished in the PCI core.
The transmit FIFOs have full flags and the receive FIFOs have empty flags. Both types of FIFOs have
programmable status flags that may be used to determine if either of the transmit FIFOs are almost full or if
either of the receive FIFOs are almost empty.