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| 型号： | QL5064-33APB456M |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封装： | PLASTIC, BGA-456 |
| 文件页数： | 31/45页 |
| 文件大小： | 635K |
| 代理商： | QL5064-33APB456M |
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2006 QuickLogic Corporation
QL5064 QuickPCI Data Sheet Rev. I
37
QL5064 External Device Pins
NOTE: Signal names that end in the character ‘N” are active-low (for example, Mst_IRDYN).
Table 19: QL5064 External Device Pins
Pin/Bus Name
Type
Function
AD[63:0]
T/S
PCI Address and Data. 32-bit multiplexed address/data bus.
CBEN[7:0]
T/S
PCI Bus Command and Byte Enables. Multiplexed bus which contains byte enables
for AD[31:0] or the Bus Command during the address phase of a PCI transaction.
PAR
T/S
PCI Parity. Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock
after address or data phases. Master drives PAR on address cycles and PCI writes.
The Target drives PAR on PCI reads.
PAR64
T/S
PCI Parity Upper DWORD. Even Parity across AD[63:32] and C/BEN[7:4] busses.
FRAMEN
S/T/S
PCI Cycle Frame. Driven active by current PCI Master during a PCI transaction.
Driven low to indicate the address cycle, driven high at the end of the transaction.
REQ64N
S/T/S
PCI Request 64-bit transfer. Driven by the PCI Master to request a 64-bit transfer.
Same signal timing as FRAMEN.
DEVSELN
S/T/S
PCI Device Select. Driven by a Target that has decoded a valid base address.
ACK64N
S/T/S
PCI Acknowledge 64-bit Transfer. Driven by a Target which has decoded a valid
base address for a 64-bit data transfer. Same timing as DEVSELN.
CLK
IN
PCI System Clock Input.
RSTN
IN
PCI System Reset Input.
REQN
T/S
PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to use the
bus. A point to point signal between the PCI Device and the System Arbiter.
GNTN
IN
PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the
PCI bus by the Arbiter. A point to point signal between the PCI device and the System
Arbiter.
PERRN
S/T/S
PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a
data parity error is detected on the AD and C/BEN busses.
SERRN
O/D
PCI System Error. Driven active when an address cycle parity error, data parity error
during a special cycle, or other catastrophic error is detected.
IDSEL
IN
PCI Initialization Device Select. Use to select a specific PCI Agent during System
Initialization.
IRDYN
S/T/S
PCI Initiator Ready. Indicates the Initiator’s ability to complete a read or write
transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN
are active.
TRDYN
S/T/S
PCI Target Ready. Indicates the Target’s ability to complete a read or write
transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN
are active.
STOPN
S/T/S
PCI Stop. Used by a PCI Target to end a burst transaction.
INTAN
O/D
Interrupt A. Asynchronous Active-Low Interrupt Request.
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