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参数资料
| 型号： | RJ80530GZ933512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 933 MHz, MICROPROCESSOR, PBGA479 |
| 封装： | MICRO, FCBGA-479 |
| 文件页数： | 16/92页 |
| 文件大小： | 1750K |
| 代理商： | RJ80530GZ933512 |
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Mobile Intel
Pentium III Processor-M Datasheet
298340-003
Datasheet
23
3.2.2
Voltage Planes
All VCC and VSS pins/balls must be connected to the appropriate voltage plane. All VCCT and VREF
pins/balls must be connected to the appropriate traces on the system electronics. In addition to the main
VCC, VCCT, and VSS power supply signals, PLL1 and PLL2 provide analog decoupling to the PLL
section. PLL1 and PLL2 should be connected according to Figure 2. Do not connect PLL2 directly to
VSS. Appendix A contains the RLC filter specification.
Figure 2. PLL RLC Filter
PLL1
PLL2
V
CCT
V0027-01
L1
C1
R1
3.2.3
Voltage Identification
There are five voltage identification balls/pins on the Mobile Intel Pentium III Processor-M. These
signals can be used to support automatic selection of VCC voltages. They are needed to cleanly support
voltage specification variations on current and future processors. VID[4:0] signals are defined in Table
VID[4:0] signals are open drain on the processor and need pullup resistors to 3.3V on the motherboard.
Please refer to the mobile VR guidelines provided by Intel for additional information.
Table 7. Mobile Intel Pentium III Processor-M VID Values
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
VID[4:0]
VCC (V)
00000
1.750
01000
1.350
10000
0.975
11000
0.775
00001
1.700
01001
1.300
10001
0.950
11001
0.750
00010
1.650
01010
1.250
10010
0.925
11010
0.725
00011
1.600
01011
1.200
10011
0.900
11011
0.700
00100
1.550
01100
1.150
10100
0.875
11100
0.675
00101
1.500
01101
1.100
10101
0.850
11101
0.650
00110
1.450
01110
1.050
10110
0.825
11110
0.625
00111
1.400
01111
1.000
10111
0.800
11111
0.600
Figure 3 shows the system level connections for the VTTPWRGD signal. Please refer to the
appropriate VR and system level guidelines provided by Intel for more details.
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